1mo
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DFT Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOE5+ years DFT experience including specification, architecture, insertion and analysis; silicon bring-up/debug/validation of DFT features; fault modeling; ATPG/MBIST/JTAG/ATE experience; strong problem-solving and communication skills.
Design/Fusion Compiler, DFT Max, SpyGlass, Modus, Tessent, TestKompress, ATPG, MBIST, JTAG, ATE
3mo
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SoC DFT Engineer
Austin or Cupertino
OnsiteFull Time
3+ YOEBS with at least 3 years of experience in silicon DFT; strong Verilog/VHDL and DFT tool knowledge.
Verilog, VHDL, Simulators, Waveform Debugging, Scripting, DFT tools
1mo
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DFT Engineer
Austin, Texas, United States
$129k-$207k/yr OnsiteFull Time
8+ YOEBSEE with 12+ years or MSEE with 8+ years, strong DFT knowledge including MBIST, scan insertion, ATPG, silicon bring-up and yield improvement, Mentor Tessent/Synopsys experience, and Perl scripting.
Mentor Tessent, Synopsys, Perl
1mo
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Principal DFT Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOE5+ years DFT implementation and verification experience including scan architectures, JTAG, memory MBIST, ATPG; Verilog/VHDL RTL knowledge; ability to handle RTL DFT changes, analyze ATPG/DRC reports, and support test pattern bring-up.
RTL, MBIST, ATPG, JTAG, TAP, ATE, Verilog, VHDL, SDF
2mo
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Semicustom DFT Strategy Lead
Austin, Texas, United States
HybridFull Time
Senior DFT and testing leader with cross-functional collaboration, roadmap development, and experience with EDA/ATE tools.
EDA tools, ATE tools, CAD tools, DFT tools, Internal DFT tools
2mo
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Principal Test Engineer/DFT Architect
Austin, Texas, United States
OnsiteFull Time
12+ YOEDefine product-level test/DFT strategy; lead cross-functional DFT efforts; mentor engineers; 12+ years in semiconductor test/DFT; strong ATE experience.
ATE, DFT, signal measurement, scripting, Python, MATLAB, SQL
3w
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Sr. Staff Engineer - DFT
Austin, Texas, United States
OnsiteFull Time
10+ YOEBS/MS in ECE/EE with 10+ years DFT experience; skilled in scan, scan compression, boundary scan, MBIST, low-power DFT, ATPG and RTL; experience with Tessent MBIST flow, Cadence Genus/Modus, and scripting (Tcl, Perl, Python).
Cadence Genus, Modus, Tessent, Tcl, Perl, Python
1w
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DFT Implementation Engineer
Austin, Texas, United States
$142k-$200k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE,5+ years DFT/SoC design experience, RTL design (Verilog/VHDL/SystemVerilog), ATPG/scan/MBIST experience, Tessent and industry DFT tool knowledge, scripting (TCL/Perl/Python).
Tessent Shell, SSN, Tessent Fast IO, ISTK, Siemens EDA (Mentor) Tessent, Synopsys DFT Compiler, Cadence Modus, ATPG, MBIST, Verilog, VHDL, SystemVerilog, TCL, Perl, Python, UPF
2mo
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Principal DFT Engineer (Silicon Engineering)
Austin or Irvine or Sunnyvale
OnsiteFull Time
10+ YOEBachelor’s in electrical/computer engineering or computer science; 10+ years in ASICs and DFT, including scan insertion and validation.
Siemens Tessent, ATPG, Verilog, SystemVerilog, UPF, Formal verification, DRC, Python, Perl, Tcl, C++
3w
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DFT Technical Leader
San Jose or Austin or New York City or New York or Washington or United States or Canada
$184k-$264k/yr HybridFull Time
10+ YOEBachelor's or Master's in Electrical/Computer Engineering, 10+ years experience in DFT, Jtag/Scan/BIST, ATPG and EDA tools, gate-level simulation and post-silicon validation experience.
Jtag, Scan, BIST, ATPG, TestMax, Tetramax, Tessent, PrimeTime, VCS, P1687, Verilog, System Verilog
1mo
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DFT Engineer (CE-64000920)
Austin or Chandler or Greensboro
HybridFull Time
2+ YOEMSEE with 2+ years or BS with relevant experience; hands-on ASIC DFT design and verification; experience with FastScan, TestKompress, TetraMAX, Test Compiler; MBIST, scan/ATPG, Verilog/SystemVerilog/VHDL; scripting (Perl, Python, TCL); strong communication.
FastScan, TestKompress, TetraMAX, Test Compiler, Verilog, SystemVerilog, VHDL, Perl, Python, TCL
1mo
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DFT Design Engineer
Austin, Texas, United States
OnsiteFull Time
2+ YOEUS citizenship required. 2+ years SoC/ASIC digital design experience focused on DFT, including scan chain insertion, compression scan, MBIST/LBIST, ATPG, JTAG/IEEE standards, Verilog testbench debugging, and familiarity with Cadence tools/flows.
Cadence tools and flows, Verilog, ATPG, MBIST, LBIST, JTAG 1149.1/6, IEEE1500, IEEE1687
2mo
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Sr. DFT Design Engineer, AWS Machine Learning Acceleration
Austin, Texas, United States
$159k-$215k/yr OnsiteFull Time
5+ YOE5+ years ASIC/SoC design; DFT, ATPG, JTAG, MBIST; scripting; collaboration with PD/architecture; RTL through silicon experience.
ATPG, JTAG, MBIST, RTL, Python, Perl, Tcl, DFT/SCAN/ATPG tools
22h
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Senior SLT Test Engineer
Austin, Texas, United States
OnsiteFull Time
Experience in semiconductor test/validation, DFT concepts, post-silicon bring-up, strong debug and root-cause analysis, proficiency with Python/Tcl/Shell, and a bachelor's degree in EE/CE or related field.
Python, Tcl, Shell, DFT, JTAG, BIST, MBIST, boundary scan, ATE, SLT, OSAT
1mo
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Senior Test Engineer
Hillsboro or Austin or Redmond or Mountain View
$120k-$235k/yr HybridFull Time
1+ YOEAdvanced degree or equivalent experience in EE/CE/CS with technical engineering experience; expertise in scan/DFT/ATPG, ATE test development (scan), silicon bring-up, debug, and yield analysis; ability to pass Microsoft background and export-control screenings.
Advantest 93K, Linux, ATPG, DFT, JTAG
17h
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Electrical Senior Principal Engineer
Round Rock, Texas, United States
$174k-$226k/yr OnsiteFull Time
12+ YOE12+ years experience delivering complex electronics from concept to production; strong debugging with oscilloscopes, logic analyzers and power instrumentation; fluency with EMI/EMC, DFM/DFT; excellent communication.
oscilloscope, logic analyzer, power instrumentation, lab instrumentation
3mo
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Senior Electrical Engineer – PCBA Schematic & Layout
Austin, Texas, United States
OnsiteFull Time
3+ YOE3+ years PCB schematic/layout experience; Bachelor's in Electrical Engineering; Proficiency in Altium Designer; multi-layer high-speed design; DFM/DFT; strong problem solving and documentation.
Altium Designer, SPICE, DFM/DFT tooling
1mo
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Software R&D Engineer, Digital Logic Synthesis - New College Grad 2026
Santa Clara or Austin
$116k-$219k/yr OnsiteFull Time
MS or PhD in EE/CS (or equivalent), experience with EDA/VLSI flows and logic synthesis, strong C++ skills, Verilog/SystemVerilog knowledge, and familiarity with synthesis/STA/DFT/power optimization techniques.
C++, Verilog, SystemVerilog, STL, Verific, Espresso, SAT solvers, GNNs, RL
18h
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Infrastructure and Tools Developer (787687)
Austin, Texas, United States
HybridFull Time
Hands-on experience with ASIC/SoC design, RTL, Verilog, UVM/SystemVerilog, front-end EDA tools, synthesis/STA/DFT, and scripting (Perl, Python, bash, csh). Strong communication and presentation skills.
Verilog, UVM, SystemVerilog, Perl, Python, bash, csh, CloudBees Jenkins, Load Sharing Facility (LSF), Slurm, Altair
18h
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Infrastructure and Tools Developer
Austin, Texas, United States
OnsiteFull Time
Several years of ASIC/SoC frontend experience with RTL/Verilog/SystemVerilog,UVM; scripting in Perl/Python/bash/csh; familiarity with synthesis, STA, DFT and front-end verification tools; BS/MS in EE/CS.
Verilog, UVM, SystemVerilog, Perl, Python, bash, csh, CloudBees Jenkins, LSF (Load Sharing Facility), Slurm, Altair