166 engineer digital design engineering jobs at 55 companies in Salinas, CA
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Digital Design Engineer
San Jose, California, United States
$166k-$229k/yr OnsiteFull Time
Master's degree in electrical, electronics, or computer engineering required. Requires C/C++ or Python, Verilog, VLSI design, signal processing, digital and analog IC design, design automation, and computer architecture knowledge.
C, C++, Python, Verilog
2mo
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Senior Engineer, Digital Design Engineering
San Jose, California, United States
$157k-$202k/yr HybridFull Time
2+ YOEMaster's in EE/CE/CS or related, 2+ years digital/mixed-signal design and verification experience, expertise in RTL, Lint, CDC, Verilog/System Verilog, Cadence or Synopsis tools, simulation, synthesis, and ASIC flow.
Cadence, Synopsis, Verilog, System Verilog, RTL, Lint, CDC
1mo
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Digital Layout Design Engineer
Santa Clara, California, United States
OnsiteFull Time
Design custom digital macros and libraries for ASICs at advanced technology nodes; collaborate with integration, CAD, circuit, and technology engineering teams.
1mo
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Digital Design Engineer
San Jose, California, United States
$130k-$200k/yr OnsiteFull Time
5+ YOEBS/MS/PhD in EE/CE,5+ years digital RTL design experience,SystemVerilog proficiency,ASIC flow and EDA tool experience,high-speed SerDes/DSP knowledge,Python/MATLAB/C++ familiarity.
System Verilog, Synopsys, Cadence, Siemens, Python, MATLAB, C++
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PMTS ASIC Digital Design IP ENGINEERING
Santa Clara, California, United States
$167k-$275k/yr OnsiteFull Time
12+ YOEBachelor's or master's degree in electrical or computer engineering, 12+ years of processor or complex SoC digital design, expert Verilog/SystemVerilog, and expertise in microarchitecture, synthesis, timing, CDC, RDC, and low-power design.
Verilog, SystemVerilog, RISC-V, ARM, MIPS, ARC, ISO 26262, DO-254, EDA
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PMTS ASIC Digital Design IP ENGINEERING
Santa Clara, California, United States
$167k-$275k/yr OnsiteFull Time
12+ YOEBachelor's or master's degree in electrical or computer engineering; 12+ years in processor, CPU, DSP, or complex SoC digital design; expert Verilog/SystemVerilog and processor microarchitecture expertise.
Verilog, SystemVerilog, EDA
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Senior Digital Design Engineer
Santa Clara or Austin or Redmond
$136k-$265k/yr OnsiteFull Time
5+ YOE5+ years experience in digital/ASIC design, degree in EE/CE or equivalent, experience with high-speed protocols (NVLink, PCI-Express, Ethernet, UCIE), RTL implementation, and ASIC design flows.
NVLink, PCI-Express, Ethernet, UCIE, RTL
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Senior HSIO Digital Design Engineer
San Jose, California, United States
$138k-$206k/yr OnsiteFull Time
3+ YOE3+ years industry experience in digital HSIO or die-to-die interfaces; BS/MS/PhD in Electrical Engineering with specified experience; knowledge of high-speed serial protocols, SI/PI, and digital/analog co-design.
AXI, CHI, CXS.B, CXL, PCIE, UA-Link
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Digital IC Design Engineer
Santa Clara, California, United States
$172k-$269k/yr OnsiteFull Time
10+ YOERequires BSEE with 12 years or MSEE with 10 years of digital/mixed-signal ASIC architecture and design experience, multiple device tape-outs, digital logic, ASIC flow, Verilog, and analog IC knowledge.
Verilog, SystemVerilog, Xcelium, Perl, Tcl, Python, MATLAB, UVM, FPGA, Palladium, DisplayPort, MIPI C-PHY, MIPI D-PHY, I2C, SPI, HDCP, DSC, STA, RTL, GDSII, ASIC, PLL, SerDes, CDC
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Senior Digital Design Engineer
Santa Clara or Austin or Redmond
$136k-$265k/yr OnsiteFull Time
5+ YOEBachelors or Master's in EE/CE or equivalent experience, 5+ years relevant experience, experience with high-speed protocols (NVLink, PCI-Express, Ethernet, UCIE), delivering high-bandwidth datapath blocks, deep ASIC design flow knowledge.
NVLink Fusion, NVLink, PCI-Express, Ethernet, UCIE, RTL, SoC
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Digital Design Engineer - New College Grad
San Jose, California, United States
$99k-$183k/yr HybridFull Time
Master's degree in EE or related field; experience with RTL coding, Verilog models, and analog/digital design; test support and chip bring-up; strong communication and team skills.
Verilog, RTL, Simulations, I2C, SPI, AHB, APB, Bench testing, ATE testing
1mo
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Digital Design RTL Engineer
Fort Collins or San Jose
$122k-$195k/yr OnsiteFull Time
8+ YOEBSEE required; 8+ years experience in SoC integration with RTL design in advanced nodes, SystemVerilog proficiency, PPA/CDC/RDC and low-power design knowledge; EMR not mentioned.
SystemVerilog
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Principal Digital Design Engineer
San Jose, California, United States
$190k-$240k/yr HybridFull Time
8+ YOEMS/PhD EE with 8+ years or BS EE with 12+ years; SOC architecture experience, bus/interface protocols, embedded memory knowledge, RTL/DFT/synthesis flow, silicon bring-up, strong communication and team skills.
AHB, APB, AXI, USB, I2C, I3C, SPI, UART, SRAM, OTP, MTP, EE/Flash, DDR DRAM, Flash
4w
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Senior Staff Engineer, Digital IC Design
Santa Clara, California, United States
$134k-$201k/yr OnsiteFull Time
5+ YOEDegree in computer or electrical engineering with 3–5+ years SOC/SoC experience, RTL design in SystemVerilog, SoC integration and timing closure, CDC/clock/reset design, and scripting with Python or Tcl.
SystemVerilog, Python, Tcl
2mo
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ASIC Digital Design, Sr Staff Engineer
Noida or Bangalore or San Jose
OnsiteFull Time
8+ YOEBSEE/MSEE with 8+ years ASIC digital design experience; expertise in UCIe/PCIe/DDR/CXL/USB, SystemVerilog/Verilog, synthesis, CDC, formal, STA, Fusion Compiler, Perforce, and scripting (Perl/Shell).
SystemVerilog, Verilog, Fusion Compiler, Perforce, Perl, Shell
1mo
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Design Engineer
San Jose, California, United States
OnsiteFull Time
3+ YOEBS/MS in Electrical/Computer Engineering (or equivalent), 3+ years SystemVerilog RTL design experience, strong digital design fundamentals, power/timing-aware practices, simulation debug, and scripting in Python/Perl/TCL.
SystemVerilog, Python, Perl, TCL, UVM, SVA
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Design Engineer (7848)
San Jose, California, United States
$156k-$156k/yr OnsiteFull Time
Master’s degree in electrical or computer engineering required. Experience with RTL, digital design, physical implementation, design verification, Perl, TCL, N16 technology, EDA tools, and semiconductor design flows.
Perl, TCL, EDA, RTL, DRC, LVS, ERC, P&R
1mo
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Sr. Staff/Staff Engineer, Digital Design
San Diego or San Jose
OnsiteFull Time
Deep RTL/SystemVerilog expertise, SoC architecture knowledge, familiarity with AXI/AHB/APB/OBI, multi-clock/multi-power-domain and timing closure experience, skills with SystemVerilog, Python, Tcl, UPF, and security technologies (Arm TrustZone, Secure Boot, PSA Level 2+); MS/PhD preferred.
SystemVerilog, Python, Tcl, UPF, AXI, AHB, APB, OBI, Arm TrustZone
2mo
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Principal Design Engineer
San Jose, California, United States
$198k-$336k/yr OnsiteFull Time
10+ YOEMS in Electrical Engineering or equivalent with 10+ years ASIC design experience; expertise in Verilog/SystemVerilog; knowledge of full digital ASIC design flow; experience with Design Compiler and PrimeTime; Python and AI-assisted tool familiarity.
Verilog, SystemVerilog, Design Compiler, PrimeTime, ncsim, Formality, Python
2mo
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Principal Design Engineer
San Jose, California, United States
$198k-$336k/yr OnsiteFull Time
10+ YOEMS in Electrical Engineering or equivalent experience, 10+ years ASIC design experience, strong Verilog/SystemVerilog skills, knowledge of full digital ASIC flow and tools (Design Compiler, PrimeTime), Python for automation, and collaboration skills.
Verilog, SystemVerilog, Design Compiler, PrimeTime, ncsim, Formality, Python
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