115 engineer digital design engineering jobs at 70 companies in San Rafael, CA
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Senior Digital Design Engineer
Vancouver or Chandler or San Francisco
$150k-$200k/yr HybridFull Time
6+ YOEBachelor's or master's degree in electrical or computer engineering, 6+ years of digital IC design experience, and hands-on Verilog or SystemVerilog RTL development for complex SoCs or ASICs.
Verilog, SystemVerilog, Synopsys, Cadence, SDC, UPF, CPF
1mo
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AI Silicon, Digital Design Engineer
Palo Alto, California, United States
OnsiteFull Time
8+ YOEB.S. or M.S. in EE/Computer Engineering, 8+ years ASIC/SoC digital design experience, Verilog RTL expertise, EDA tool proficiency, synthesis/timing/LEC experience, and mentorship/communication skills.
Verilog, RTL, EDA tools, Logical Equivalence Checking (LEC), Clock Domain Crossing (CDC), Reset Domain Crossing (RDC)
1mo
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Machine Learning Digital Design Engineer
Sunnyvale, California, United States
$178k-$250k/yr OnsiteFull Time
8+ YOEBachelor's degree or equivalent, 8+ years hardware design experience for production silicon, expertise in digital µarchitecture, RTL coding, micro-architecture development, and cross-functional technical communication.
RTL, SoC, ASIC, DSP, microcontrollers
1w
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Senior RTL Design Engineer, Digital Signal Processing
Sunnyvale, California, United States
$163k-$236k/yr OnsiteFull Time
8+ YOEBachelor's degree in electrical or computer engineering, 8 years of DSP or high-speed digital logic design, and experience with communication systems, PHY, MATLAB, Python, or C++.
MATLAB, Python, C++, Design Compiler, Genus, PrimeTime, Tempus, Spyglass, Conformal, SerDes, SystemC
1w
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Design Engineer III
Menlo Park or Sunnyvale
$140k-$150k/yr HybridFull Time
5+ YOERequires a BS in electrical/computer engineering or computer science, 5+ years of experience, SystemVerilog/UVM verification, coverage and SVA, RTL debug, simulators, Python or Perl, and digital design fundamentals.
SystemVerilog, UVM, VCS, Xcelium, Questa, Verdi, Python, Perl, PrimeTime PX (PTPX), PrimePower, UPF, Palladium, Zebu, RTL-to-GDSII
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Senior Design Engineer
Mountain View or Redmond
$120k-$235k/yr HybridFull Time
5+ YOERequires a doctorate plus 1+ year, master's plus 4+ years, bachelor's plus 5+ years, or equivalent experience in electrical, computer, or related engineering. Preferred expertise includes digital design, RTL, NoC, ASIC/SoC, synthesis, and post-silicon debug.
Intellectual Property (IP), Register Transfer Level (RTL), System on Chip (SOC), Verilog, SystemVerilog, Clock Domain Crossing (CDC), NoCs, ASIC, CPU
2mo
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Electrical Design Engineer
Palo Alto, California, United States
$130k-$179k/yr HybridFull Time
7+ YOEBS/MS in Electrical Engineering; 7+ years PCB design experience; strong analog/digital/power circuitry; EMI/SI knowledge; lab test experience; good communication.
PSpice, LTSpice, Hyperlynx, Oscilloscopes, Logic analyzers, PCB design tools, PCB layout constraints
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Hardware Design Engineer
Tempe or San Jose or San Francisco or New York City
$133k-$210k/yr OnsiteFull Time
4+ YOEBachelor's degree or equivalent in electrical or computer engineering, 4+ years in high-speed digital board design and FPGA/RTL development, US citizenship, Secret clearance eligibility, and up to 10% travel.
SystemVerilog, Verilog, VHDL, AMD Vivado, Intel Quartus, Synopsys Synplify, Mentor Xpedition, Cadence, Altium, HyperLynx, Python, TCL, Perl, ModelSim, Questa, Git, Claude Code, Copilot, DDR4, SERDES, UART, I2C, SPI, LVDS, FPGA, RTL, SoC, ADC, DAC, CI/CD, AI
2mo
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Baseband Hardware Design Engineer
Sunnyvale, California, United States
OnsiteFull Time
Experience with computer system architecture and digital design; architecture, design, implementation, and integration of baseband systems; strong collaboration with cross-functional engineering teams.
1mo
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Senior Logic Design Engineer
Sunnyvale, California, United States
$170k-$250k/yr OnsiteFull Time
10+ YOEBachelor's in Electrical/Computer Engineering, 10+ years front-end digital SoC experience, Verilog/SystemVerilog and synthesis expertise, embedded/mixed-mode design and strong debugging and communication skills.
Verilog, SystemVerilog
3mo
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PCB Design Engineer – Altium / Schematic & Layout
Saratoga, California, United States
$130k-$200k/yr OnsiteFull Time
PCB design engineer with Altium, multi-layer high-speed digital/mixed-signal boards; DFx focus; not RF design.
Altium Designer
2mo
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Senior Hardware Design Engineer
Newark, California, United States
$130k-$150k/yr OnsiteFull Time
10+ YOEBachelor's in electrical engineering, 10+ years designing high-speed digital/analog circuitry and complex high-density PCBs, 5+ years designing fine-pitch boards, hands-on validation and debugging, proficiency with Python and C, experience with DDR4/DDR5 and PCIe Gen 5/6.
Python, C, DDR4, DDR5, PCIe Gen 5/6, SERDES, Protocol Analyzers, Oscilloscopes, Logic Analyzers, EVT, DVT
1w
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Circuit Design Engineer III, Avionics
Sunnyvale, California, United States
$123k-$228k/yr OnsiteFull Time
3+ YOEBachelor's degree in electrical engineering or related field, 3+ years of experience designing digital or analog circuits and performing electronics analysis; U.S. citizenship required for DoD Secret clearance.
Zuken, PSPICE, Saber, SPICE, FPGA, Printed Wiring Board
3mo
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Senior Rail Track Design Engineer
Coral Gables or New York City or Tampa or San Francisco or Houston or Los Angeles or Chicago or Pensacola or Dallas
HybridFull Time
8+ YOESenior track design engineer with 8+ years rail experience, PE licensure, civil engineering degree; BIM/Digital design tools proficiency; lead complex rail projects in the US.
Bentley OpenRail, OpenRoads, InRoads, MicroStation, Civil 3D
2w
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Signal Integrity Design Engineer
Sunnyvale, California, United States
$160k-$230k/yr OnsiteFull Time
10+ YOEBachelor's degree in electrical or computer engineering, 10+ years simulating high-speed SerDes PCB channels, Ansys HFSS or Dassault CST expertise, TDR/VNA and oscilloscope measurement skills, and high-speed digital design knowledge.
Ansys HFSS, Dassault CST, TDR, VNA, oscilloscopes, Mentor HyperLynx, HSpice, Cadence Allegro, C, Python, Matlab
2mo
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Mixed Signal Logic Design Engineer
Hillsboro or San Francisco or Phoenix
$142k-$269k/yr OnsiteFull Time
3+ YOEBS or MS with relevant experience in electrical/computer engineering; SystemVerilog; digital and mixed-signal design; multi-clock-domain designs; independent work; team leadership optional.
SystemVerilog, Python, Perl, Bash, CDC analysis, Linting, AMS simulation, Scripting
2mo
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Hardware Design Engineer (Santa Clara, CA, US)
Santa Clara or Palo Alto
$65k-$169k/yr OnsiteFull Time
7+ YOEBachelor's in Electrical/Electronics/Computer Engineering, 7+ years hardware design experience (automotive preferred); analog/digital circuit design; PCB tools (Altium, Cadence, OrCAD); signal/power/thermal management; Ethernet, PCIe, MIPI, GMSL; high-speed validation and debugging.
Altium, Cadence, OrCAD, Ethernet, PCIe, MIPI, GMSL
1w
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Senior IC&E Reactor Protection System Design Engineer
Alameda, California, United States
$141k-$165k/yr OnsiteFull Time
6+ YOEBachelor's degree in electrical or computer engineering, 6 years of relevant engineering experience, regulated or high-reliability environment experience, analog and digital circuit design, schematic capture, PCB design, and lab debugging.
Altium, Cadence, Ki Cad, FPGA, HDL, Verilog
1mo
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Electrical Design Engineer Level 2 / 3
Sunnyvale, California, United States
$92k-$138k/yr OnsiteFull Time
2+ YOEDesign, develop, and test analog/digital circuitry, cable and data acquisition systems; troubleshoot electromechanical control systems; must be U.S. citizen able to obtain Secret clearance.
Oscilloscope, DMM, IR tester, MATLAB, Simulink, LabVIEW, LabWindows, C, C++, C#, FPGA
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Senior Design Verification Engineer
Sunnyvale, California, United States
$154k-$311k/yr HybridFull Time
Bachelor's in EE/CE/CS required; coursework in digital logic and HDLs; familiarity with verification concepts, SystemVerilog/UVM, scripting (Python/Tcl/Perl/Shell); strong analytical and communication skills.
Verilog, VHDL, SystemVerilog, Python, C, C++, UVM, Synopsys VCS, Cadence Xcelium, Mentor Questa, Tcl, Perl, Shell
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