HiringCafe
Join our community

75 formal verification engineer jobs at 34 companies in San Jose, CA

3d
Save
Mark Applied
Hide
Formal Verification Engineer
Austin or Boston or Santa Clara
$127k-$217k/yr HybridFull Time
AMD
AMDNASDAQ: AMD: Designs and manufactures computer processors and graphics technology.
8+ YOERequires 8+ years in design verification focused on formal verification, VC Formal or JasperGold, SystemVerilog Assertions, TCL/Python/Perl, and a bachelor's or master's degree in computer or electrical engineering.
VC Formal, JasperGold, SystemVerilog Assertions (SVA), TCL, Python, Perl
Job PostingView all
2mo
Save
Mark Applied
Hide
Formal Verification Engineer
San Jose, California, United States
$150k-$350k/yr OnsiteFull Time
Alpha Design AI
Alpha Design AI: AI-native EDA platform for semiconductor design and verification.
Deep formal verification expertise, experience with assertion-based verification and proof debugging, proficiency scripting in Python or Tcl, and hands-on use of formal EDA tools to verify RTL and production IP.
JasperGold, VC Formal, Questa Formal, SystemVerilog Assertions (SVA), Python, Tcl
Job PostingView all
2mo
Save
Mark Applied
Hide
Formal Verification Engineer
Mountain View, California, United States
$120k-$425k/yr HybridFull Time
MatX
MatX: Designing specialized AI chips for large language model workloads.
Hands-on formal verification and theorem-proving experience for RTL, memory, interconnects and compiler correctness; SVA/PSL, model checking, and interactive provers experience required.
JasperGold, VC-Formal, SymbiYosys, Lean 4, Coq, Isabelle/HOL, Agda, CompCert
Job PostingView all
4d
Save
Mark Applied
Hide
Formal Verification Engineer
Palo Alto or London
OnsiteFull Time
Harmonic
Harmonic: Developing artificial intelligence models for formal mathematical reasoning.
Bachelor's degree or equivalent experience; verification or theorem-proving experience; formal methods and mathematical logic expertise; proof-assistant proficiency; autonomous risk management and strong customer communication.
Lean 4, Coq, Isabelle, Agda
Job PostingView all
3w
Save
Mark Applied
Hide
Senior Formal Verification Engineer
Santa Clara, California, United States
$200k-$500k/yr OnsiteFull Time
Velaura AI
Velaura AI: Developing ultra-low-power silicon and IP for AI accelerators.
10+ YOE10+ years in functional verification with hands-on formal verification, SVA property development, experience with JasperGold/VC Formal/Questa Formal/OneSpin, scripting/automation, strong computer architecture and floating-point knowledge.
SystemVerilog Assertions (SVA), JasperGold, VC Formal, Questa Formal, OneSpin, C, C++, SystemC
Job PostingView all
2mo
Save
Mark Applied
Hide
Senior Formal Verification Engineer
Santa Clara or Austin
$136k-$265k/yr OnsiteFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs GPU-accelerated computing and artificial intelligence hardware.
5+ YOE5+ years experience with formal verification of RTL; degree in CS/CE/EE/Mathematics or equivalent experience; experience with Verilog/SystemVerilog, formal tools, abstraction techniques, and scripting (TCL, Perl, Python).
Verilog, SystemVerilog, TCL, Perl, Python
Job PostingView all
2mo
Save
Mark Applied
Hide
Senior Formal Verification Engineer
Santa Clara or Austin
$136k-$265k/yr OnsiteFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs graphics processing units and artificial intelligence hardware.
5+ YOE5+ years experience with formal verification; BS/MS/PhD in CS/CE/EE/Math or equivalent; experience with Verilog/System Verilog, formal tools, abstraction techniques; scripting with TCL/Perl/Python; strong analytical and communication skills.
Verilog, System Verilog, TCL, Perl, Python
Job PostingView all
1mo
Save
Mark Applied
Hide
Formal Design Verification Engineer
Raleigh or Austin or Hillsboro or Mountain View or Redmond
$120k-$235k/yr HybridFull Time
Microsoft
MicrosoftNASDAQ: MSFT: Develops software, services, devices, and cloud computing solutions.
1+ YOEDegree in EE/CS or equivalent plus technical engineering experience; formal verification, protocol and IP verification experience; ability to pass Microsoft Cloud Background Check and export-control screening.
Coherent Hub Interface (CHI), Advanced Microcontroller Bus Architecture (AMBA), PCIe, CXL, Universal Verification Methodology (UVM), System Verilog Test Bench (SVTB), Python
Job PostingView all
2mo
Save
Mark Applied
Hide
Formal Verification - DV
San Jose, California, United States
OnsiteFull Time
Etched
Etched: Designs specialized AI chips optimized for transformer architectures.
5+ YOE5+ years design verification with hands-on formal verification experience; strong SystemVerilog/SVA skills; experience with commercial formal tools; deep digital design and SoC interface knowledge; strong RTL/debug skills.
SystemVerilog, SystemVerilog Assertions, UVM, Cadence JasperGold, Synopsys VC Formal, Siemens Questa Formal, Python, TCL, Perl
Job PostingView all
2mo
Save
Mark Applied
Hide
DV Formal Verification
Mountain View, California, United States
$200k-$420k/yr OnsiteFull Time
DensityAI
DensityAI: Designing custom AI hardware accelerators for large language models.
8+ YOEMaster's degree + 8 years formal verification experience; expertise in SVA/PSL property authoring, proof strategies, industry formal tools, debugging proof failures, and collaborating with RTL designers.
Synopsys VC Formal, Cadence Jasper
Job PostingView all
2w
Save
Mark Applied
Hide
ASIC Formal Verification Engineer, Google Cloud
Sunnyvale, California, United States
$138k-$197k/yr OnsiteFull Time
Google
GoogleNASDAQ: GOOGL: Provides online search, advertising, cloud computing, and consumer electronics.
4+ YOEBachelor's or equivalent, 4+ years formal and design verification experience, SystemVerilog/Verilog, experience with formal verification tools, scripting experience, strong communication and collaboration.
SystemVerilog, Verilog, Jasper, VC Formal, Questa Formal, 360-DV
Job PostingView all
1w
Save
Mark Applied
Hide
CPU Formal Verification Engineer
Santa Clara, California, United States
$142k-$213k/yr OnsiteFull Time
Qualcomm
QualcommNASDAQ: QCOM: Designs and manufactures semiconductors and wireless telecommunications products.
2+ YOEBachelor's degree in EE, computer engineering, or computer science plus 2+ years' relevant experience, or master's plus 1+ year, or PhD; formal methods, model checking, assertions, HDL, and programming experience.
JasperGold, VC Formal, ACL2, HOL, C++, Python, TCL, Hardware Description Languages
Job PostingView all
2mo
Save
Mark Applied
Hide
Formal Verification Engineer
Mountain View, California, United States
$140k-$420k/yr HybridFull Time
MatX
MatX: Developing custom silicon chips optimized for large language models.
0+ YOEHands-on hardware model checking with SVA/PSL; experience with interactive theorem provers (Lean, Coq, Isabelle/HOL); embedding languages/IR into provers; familiarity with compiler correctness proofs.
JasperGold, VC-Formal, Lean 4, Rocq, Isabelle/HOL, SVA/PSL, Coq, Agda
Job PostingView all
3w
Save
Mark Applied
Hide
Sr. Formal Verification Engineer, Annapurna Labs
Austin or Cupertino
$159k-$248k/yr OnsiteFull Time
Amazon
AmazonNASDAQ: AMZN: Global online retail and cloud computing technology provider.
7+ YOEBachelor's in CS/EE,7+ years formal verification experience as IP/block owner, expertise in abstraction and end-to-end checking, RTL and microarchitecture comprehension, and coding/scripting skills.
C, C++, C#, Node.JS, Java, Python, PHP, Ruby
Job PostingView all
3mo
Save
Mark Applied
Hide
Formal Verification - AI/ML Engineer
Austin or Cupertino
HybridFull Time
Apple
AppleNASDAQ: AAPL: Designs and sells consumer electronics, software, and online services.
10+ YOEBachelor's degree and 10+ years of experience; strong AI/ML, LLMs, Python, ML frameworks; domain knowledge in formal methods; good communication and self-direction.
Python, PyTorch, LangChain, LlamaIndex, Hugging Face, RAG, LLM tooling
Job PostingView all
1mo
Save
Mark Applied
Hide
Senior Staff Engineer, GPU Design Verification (Formal Verification)
San Jose, California, United States
$198k-$297k/yr OnsiteFull Time
Samsung Electronics
Samsung ElectronicsKorea Exchange: 005930: Develops and manufactures consumer electronics, semiconductors, and mobile devices.
8+ YOE8+ years verification experience (formal verification focus), proficiency in formal methods, System Verilog/SVA, Python/Perl/C++, EDA formal tools, strong debugging and architecture knowledge; BS/MS/PhD in CS/CE/related.
Python, Perl, C/C++, System Verilog, System Verilog Assertions (SVA), Confluence, JIRA, Universal Verification Methodology (UVM), UPF
Job PostingView all
1mo
Save
Mark Applied
Hide
Senior FPGA Design Verification Engineer
Sunnyvale, California, United States
$152k-$257k/yr OnsiteFull Time
Intuitive
IntuitiveNASDAQ: ISRG: Robotic-assisted systems for minimally invasive surgery.
Advanced knowledge of HVL/UVM and HDL (SystemVerilog, Verilog); experience with coverage-driven verification, constrained-random testing, testbench development, scripting (Perl/Python); experience with emulation/FPGA prototyping, formal methods and ML-assisted verification is a plus.
HVL, UVM, SystemVerilog, Verilog, Perl, Python, FPGA, Emulation, Formal
Job PostingView all
1mo
Save
Mark Applied
Hide
ASIC Engineer, Design Verification
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
Meta
MetaNASDAQ: META: Develops social networking platforms and virtual reality technologies.
6+ YOEBachelor's in CS/CE or equivalent; 6+ years SystemVerilog/UVM or C/C++ verification and IP/SoC level verification experience; EDA tools and scripting (Python, TCL, Perl, Shell).
SystemVerilog, UVM, C, C++, Python, TCL, Perl, Shell, Mercurial, Hg, Git, SVN, SV Assertions, Formal, Emulation, PCIe, RoCE, DDR, HBM, Ethernet
Job PostingView all
1w
Save
Mark Applied
Hide
Digital Verification Engineer
South San Francisco, California, United States
$131k-$243k/yr OnsiteFull Time
Neuralink
Neuralink: Developing implantable brain-computer interfaces to restore human capabilities.
3+ YOEMinimum 3 years digital ASIC verification experience; strong SystemVerilog; automation scripting (Python, Perl, Makefile, Tcl, UNIX shell); code coverage and regression setup; familiarity with SystemC/C++, UVM, formal and low-power verification preferred.
SystemVerilog, Python, Perl, Makefile, Tcl, UNIX shell, SystemC, C++, IEEE-1801 (UPF), UVM, ARM, RISC-V, AMBA, FPGA
Job PostingView all
3mo
Save
Mark Applied
Hide
Senior Debug Verification Engineer
San Jose, California, United States
$149k-$215k/yr OnsiteFull Time
Altera
Altera: Manufacturer of field-programmable gate arrays and programmable logic devices.
8+ YOE8+ years ASIC/design verification; SystemVerilog; UVM and formal verification; Linux/Unix scripting with Perl or Python; strong cross-site collaboration.
SystemVerilog, UVM, Formal verification, Linux, Perl, Python, Emulation, JTAG, PCIe, USB
Job PostingView all

Explore Jobs

Expand Your Job Search