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84 formal verification engineer jobs at 36 companies in Santa Clara, CA

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Formal Verification Engineer
San Jose, California, United States
$150k-$350k/yr OnsiteFull Time
ChipAgents
ChipAgents: Private agentic-AI software helping semiconductor design and verification engineers design, verify, and debug chips.
Deep formal verification expertise, experience with assertion-based verification and proof debugging, proficiency scripting in Python or Tcl, and hands-on use of formal EDA tools to verify RTL and production IP.
JasperGold, VC Formal, Questa Formal, SystemVerilog Assertions (SVA), Python, Tcl
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3mo
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Formal Verification Engineer
Mountain View, California, United States
$120k-$425k/yr HybridFull Time
MatX
MatX: AI semiconductor designing high-throughput chips for large language models and frontier AI labs.
Hands-on formal verification and theorem-proving experience for RTL, memory, interconnects and compiler correctness; SVA/PSL, model checking, and interactive provers experience required.
JasperGold, VC-Formal, SymbiYosys, Lean 4, Coq, Isabelle/HOL, Agda, CompCert
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Formal Verification Engineer
Palo Alto or London
OnsiteFull Time
Harmonic
Harmonic: AI research lab building a formally verified mathematical reasoning engine for mathematicians, researchers, and students.
Bachelor's degree or equivalent experience; verification or theorem-proving experience; formal methods and mathematical logic expertise; proof-assistant proficiency; autonomous risk management and strong customer communication.
Lean 4, Coq, Isabelle, Agda
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Senior Formal Verification Engineer
Santa Clara, California, United States
$200k-$500k/yr OnsiteFull Time
Velaura AI
Velaura AI: Private AI compute infrastructure developing ultra-low-power silicon and software for data centers and Physical AI.
10+ YOE10+ years in functional verification with hands-on formal verification, SVA property development, experience with JasperGold/VC Formal/Questa Formal/OneSpin, scripting/automation, strong computer architecture and floating-point knowledge.
SystemVerilog Assertions (SVA), JasperGold, VC Formal, Questa Formal, OneSpin, C, C++, SystemC
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Senior Formal Verification Engineer
Santa Clara or Austin
$136k-$265k/yr OnsiteFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Computing platform for AI and accelerated graphics.
5+ YOE5+ years experience with formal verification of RTL; degree in CS/CE/EE/Mathematics or equivalent experience; experience with Verilog/SystemVerilog, formal tools, abstraction techniques, and scripting (TCL, Perl, Python).
Verilog, SystemVerilog, TCL, Perl, Python
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Senior Formal Verification Engineer
Santa Clara or Austin
$136k-$265k/yr OnsiteFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Computing platform for AI and accelerated graphics.
5+ YOE5+ years experience with formal verification; BS/MS/PhD in CS/CE/EE/Math or equivalent; experience with Verilog/System Verilog, formal tools, abstraction techniques; scripting with TCL/Perl/Python; strong analytical and communication skills.
Verilog, System Verilog, TCL, Perl, Python
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Formal Design Verification Engineer
Raleigh or Austin or Hillsboro or Mountain View or Redmond
$120k-$235k/yr HybridFull Time
Microsoft
MicrosoftNASDAQ: MSFT: Multinational technology providing software, cloud, and AI solutions.
1+ YOEDegree in EE/CS or equivalent plus technical engineering experience; formal verification, protocol and IP verification experience; ability to pass Microsoft Cloud Background Check and export-control screening.
Coherent Hub Interface (CHI), Advanced Microcontroller Bus Architecture (AMBA), PCIe, CXL, Universal Verification Methodology (UVM), System Verilog Test Bench (SVTB), Python
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Formal Verification - DV
San Jose, California, United States
OnsiteFull Time
Etched
Etched: Private semiconductor startup building AI inference chips, racks, and software for frontier-model customers.
5+ YOE5+ years design verification with hands-on formal verification experience; strong SystemVerilog/SVA skills; experience with commercial formal tools; deep digital design and SoC interface knowledge; strong RTL/debug skills.
SystemVerilog, SystemVerilog Assertions, UVM, Cadence JasperGold, Synopsys VC Formal, Siemens Questa Formal, Python, TCL, Perl
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DV Formal Verification
Mountain View, California, United States
$200k-$420k/yr OnsiteFull Time
DensityAI
DensityAI: Semiconductor startup building full-stack AI accelerators for frontier-scale large language model inference.
8+ YOEMaster's degree + 8 years formal verification experience; expertise in SVA/PSL property authoring, proof strategies, industry formal tools, debugging proof failures, and collaborating with RTL designers.
Synopsys VC Formal, Cadence Jasper
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Sr. Formal Verification Engineer, Amazon Leo
Austin or Sunnyvale or Redmond or San Diego
$159k-$248k/yr OnsiteFull Time
Kuiper Systems
Kuiper SystemsNasdaq Global Select Market: AMZN: Developing a low Earth orbit satellite network to deliver high-speed, low-latency broadband internet connectivity.
8+ YOEBachelor's degree and 8+ years of ASIC/SoC design verification experience focused on formal verification; JasperGold or Questa Formal, SVA, SystemVerilog, UVM, and AI/LLM workflow proficiency required.
JasperGold, Questa Formal, SystemVerilog Assertions (SVA), SystemVerilog, UVM, Python, TCL, Perl, AI, LLM, CI/CD
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Senior Formal Verification Engineer
Santa Clara or Austin
$136k-$265k/yr OnsiteFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Computing platform for AI and accelerated graphics.
5+ YOEBS, MS, PhD, or equivalent experience in CS, CE, EE, or Mathematics; 5+ years of experience; GPU/CPU architecture, Verilog/SystemVerilog, formal tools, abstraction techniques, and TCL, Perl, or Python scripting.
Verilog, SystemVerilog, TCL, Perl, Python, RTL
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ASIC Formal Verification Engineer, Google Cloud
Sunnyvale, California, United States
$138k-$197k/yr OnsiteFull Time
Google
GoogleNASDAQ: GOOG, GOOGL: Global technology specializing in internet-related services and products.
4+ YOEBachelor's or equivalent, 4+ years formal and design verification experience, SystemVerilog/Verilog, experience with formal verification tools, scripting experience, strong communication and collaboration.
SystemVerilog, Verilog, Jasper, VC Formal, Questa Formal, 360-DV
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CPU Formal Verification Engineer
Santa Clara, California, United States
$142k-$213k/yr OnsiteFull Time
Qualcomm Technologies, Inc.
Qualcomm Technologies, Inc.: Developing semiconductor, wireless, connectivity, automotive, AI, and computing technologies for device and enterprise customers.
2+ YOEBachelor's degree in EE, computer engineering, or computer science plus 2+ years' relevant experience, or master's plus 1+ year, or PhD; formal methods, model checking, assertions, HDL, and programming experience.
JasperGold, VC Formal, ACL2, HOL, C++, Python, TCL, Hardware Description Languages
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Formal Verification - AI/ML Engineer
Austin or Cupertino
HybridFull Time
Apple
AppleNASDAQ: AAPL: Designing and manufacturing consumer electronics, software, and digital services.
10+ YOEBachelor's degree and 10+ years of experience; strong AI/ML, LLMs, Python, ML frameworks; domain knowledge in formal methods; good communication and self-direction.
Python, PyTorch, LangChain, LlamaIndex, Hugging Face, RAG, LLM tooling
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Senior Staff Engineer, GPU Design Verification (Formal Verification)
San Jose, California, United States
$198k-$297k/yr OnsiteFull Time
Samsung Electronics
Samsung ElectronicsKorea Exchange: 005930: Global leader in technology, semiconductors, and consumer electronics.
8+ YOE8+ years verification experience (formal verification focus), proficiency in formal methods, System Verilog/SVA, Python/Perl/C++, EDA formal tools, strong debugging and architecture knowledge; BS/MS/PhD in CS/CE/related.
Python, Perl, C/C++, System Verilog, System Verilog Assertions (SVA), Confluence, JIRA, Universal Verification Methodology (UVM), UPF
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Design Verification Engineer
Santa Clara or Folsom or Austin
$166k-$250k/yr HybridFull Time
AMD
AMDNASDAQ: AMD: Leader in high-performance computing, graphics, and visualization technologies.
6+ YOEExperienced verification engineer with SystemVerilog, UVM, C/C++, Python or Perl, DDR memory verification, formal verification, and cross-functional hardware, firmware, and software collaboration experience.
SystemVerilog, UVM, C, C++, Python, Perl, DDR5, LPDDR5, LPDDR6, DFI, DIMMs, RTL, BIOS, GLS, NLP, XPROP, VIPs, BFMs
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Technical Staff Engineer - Verification
Chandler or San Jose or San Jose or Roseville or Austin
$91k-$232k/yr OnsiteFull Time
Microchip Technology
Microchip TechnologyNASDAQ: MCHP: A leading provider of smart, connected, and secure embedded control solutions.
12+ YOEBS or MS in electrical/electronic engineering and 12+ years verifying complex SoC designs. Requires SystemVerilog, UVM, formal verification, methodology development, automation, scripting, and SoC architecture expertise.
SystemVerilog, UVM, Python, TCL/TK, C, C++, Siemens, Cadence, Synopsys, Git, Perforce, svn, ARM, RISC-V, PCIe, DDR4, DDR5, LPDDR4X, MIPI DSI, MIPI CSI, Ethernet MAC, USB, FPGA, SoC, RTL, GDS
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Senior FPGA Design Verification Engineer
Sunnyvale, California, United States
$152k-$257k/yr OnsiteFull Time
Intuitive
IntuitiveNASDAQ: ISRG: Global leader in robotic-assisted and minimally invasive surgery.
Advanced knowledge of HVL/UVM and HDL (SystemVerilog, Verilog); experience with coverage-driven verification, constrained-random testing, testbench development, scripting (Perl/Python); experience with emulation/FPGA prototyping, formal methods and ML-assisted verification is a plus.
HVL, UVM, SystemVerilog, Verilog, Perl, Python, FPGA, Emulation, Formal
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ASIC Engineer, Design Verification
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
Meta
MetaNASDAQ: META: Builds technologies that help people connect, find communities, and grow businesses.
6+ YOEBachelor's in CS/CE or equivalent; 6+ years SystemVerilog/UVM or C/C++ verification and IP/SoC level verification experience; EDA tools and scripting (Python, TCL, Perl, Shell).
SystemVerilog, UVM, C, C++, Python, TCL, Perl, Shell, Mercurial, Hg, Git, SVN, SV Assertions, Formal, Emulation, PCIe, RoCE, DDR, HBM, Ethernet
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Digital Verification Engineer
South San Francisco, California, United States
$131k-$243k/yr OnsiteFull Time
Neuralink
Neuralink: Private neurotechnology developing implantable brain-computer interfaces for people with unmet medical needs.
3+ YOEMinimum 3 years digital ASIC verification experience; strong SystemVerilog; automation scripting (Python, Perl, Makefile, Tcl, UNIX shell); code coverage and regression setup; familiarity with SystemC/C++, UVM, formal and low-power verification preferred.
SystemVerilog, Python, Perl, Makefile, Tcl, UNIX shell, SystemC, C++, IEEE-1801 (UPF), UVM, ARM, RISC-V, AMBA, FPGA
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