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FPGA Engineer
El Segundo or Los Angeles or Washington or San Francisco or Seattle or London
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor's in a relevant field, 5+ years FPGA RTL design experience, Verilog/SystemVerilog, AXI protocols, Vivado and SoC FPGA experience, Bash/Python scripting, U.S. Person required.
Verilog, SystemVerilog, AXI4, AXI4-Lite, AXI4-Stream, Vivado Design Suite, Zynq, Ultrascale, Ultrascale+, Versal, TCP, UDP, IP, I2C, JTAG, UART, SPI, CAN, Bash, Python, Simulink, MATLAB, C, C++, SystemC, Chisel, VHDL, git, Bitbucket CI, Jenkins
1mo
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FPGA Design Engineer
Irvine, California, United States
$100k-$140k/yr OnsiteFull Time
2+ YOEBS in EE or CS with 2+ years FPGA design; Xilinx FPGAs, SoCs, Vivado; TCL or Python; U.S. Person; background check and drug test.
Xilinx FPGAs, Vivado IDE, Tcl, Python, MATLAB, FPGA Design
3d
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Senior FPGA Engineer
Playa Vista, California, United States
$137k-$193k/yr OnsiteFull Time
5+ YOEBachelor's degree in EE/CE/Physics, 5+ years FPGA design experience, strong VHDL/Verilog/SystemVerilog skills, familiarity with FPGA toolchains, high-speed interfaces, MATLAB/Python/C/C++, and lab test equipment; ability to obtain Top Secret clearance.
VHDL, Verilog, SystemVerilog, Xilinx, AMD, Intel/Altera, MATLAB/Simulink, Python, C, C++, JESD204, PCIe, Ethernet, SPI, UART, logic analyzer, oscilloscope, spectrum analyzer
2w
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Sr. FPGA Engineer I/II
Long Beach, California, United States
$143k-$239k/yr OnsiteFull Time
5+ YOEBachelor's in engineering, 5+ (I) or 8+ (II) years FPGA firmware development experience, VHDL proficiency, FPGA design fundamentals, and U.S. citizenship or equivalent export-authority eligibility for U.S. roles.
VHDL, Xilinx, Microchip, UVM, VUnit, GIT, JIRA, GigE, PCIe, SPI, UART, I2C, CAN, DWCCA
1mo
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Senior FPGA Engineer
Hawthorne or El Segundo or Los Angeles
$160k-$250k/yr OnsiteFull Time
8+ YOEBachelor’s in CE/EE/CS, 8+ years FPGA development with SystemVerilog or VHDL, familiarity with Xilinx Vivado/Vitis, experience with high-speed I/O and board bring-up, strong timing and RTL skills.
SystemVerilog, VHDL, Xilinx Vivado, Vitis, Xilinx Zynq Ultrascale+ MPSoC, C/C++, embedded Linux
2w
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Senior FPGA Engineer
Long Beach, California, United States
$148k-$222k/yr OnsiteFull Time
5+ YOEBachelors in EE/Computer Eng or related; 5+ years FPGA development and high-speed digital systems experience in mission-critical applications; RTL/verification/synthesis/timing expertise; cross-functional collaboration skills.
VHDL, Verilog, SystemVerilog, SpinalHDL, Chisel, Vitis, SystemC, Simulink, RISC-V, AMD Xilinx, Intel, Microchip, CI/CD
1w
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Staff FPGA Engineer, EW
Costa Mesa, California, United States
$220k-$292k/yr OnsiteFull Time
Design and verify FPGA/DSP modules on AMD/Xilinx SoC/FPGA platforms; experience with HDL (VHDL/Verilog), high-speed digital interfaces (PCIe, JESD, Aurora), Linux development, Git and CI/CD; eligible for U.S. Secret clearance; mentoring experience.
AMD, Xilinx, VHDL, Verilog, Linux, Git, TCL, CI/HITL, PCIE, JESD, Aurora, AMD AIE
2mo
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Senior FPGA Engineer
Torrance, California, United States
$143k-$176k/yr OnsiteFull Time
5+ YOE5+ years FPGA design, verification, and testing; embedded processing experience; RF application knowledge.
Vivado, Quartus, Matlab, Simulink, HDL Coder, UVM, SystemVerilog, AXI, AXI-Stream, Embedded Linux
1mo
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Engineer/ Principal Engineer Software - FPGA Developer
El Segundo, California, United States
$92k-$138k/yr OnsiteFull Time
0+ YOESTEM degree required (B.S./M.S./Ph.D. combinations accepted with varying experience), ability to obtain Secret clearance, FPGA development experience including simulation, place-and-route, lab/SIL integration, and FPGA-SoC integration.
1w
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FPGA Design Engineer
Long Beach, California, United States
$135k-$225k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE,5+ years FPGA development with AMD/Xilinx platforms,expertise with Vivado/Vitis and HDL,experience with PCIe/Ethernet/SerDes,hardware/software integration and production bring-up.
Xilinx Vivado, Vitis, Vivado ILA, VIO, Git, Python, TCL, ModelSim, Vivado Simulator, PetaLinux
2w
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FPGA Electrical Engineer III
Altadena, California, United States
$131k-$183k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
5+ YOEBS in Electrical/Computer Engineering, 5+ years hardware development across product lifecycle, SystemVerilog/Verilog proficiency, SoC and FPGA experience, knowledge of timing, AXI/AHB, synthesis, simulation, and avionics integration.
SystemVerilog, Verilog, Microchip Libero, Python, Linux shell scripting, Windows shell scripting, assembly language, C, C++, MATLAB, Simulink, SPICE, Altium, AXI, AHB
3mo
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Senior/Principal FPGA Design Engineer
Calabasas or Burnaby or Austin
$139k-$232k/yr OnsiteFull Time
8+ YOEBachelors or Masters in EE/CE; 8+ years in FPGA; strong VHDL/SystemVerilog; excellent communication; team leadership potential.
VHDL, SystemVerilog, Ethernet, PCIe, Interlaken, DDR5, RLDRAM3, SerDes, Tcl, Perl, Python
1mo
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Staff FPGA Design Engineer
Irvine, California, United States
$150k-$190k/yr OnsiteFull Time
8+ YOEBachelor's in EE/CE, 8+ years FPGA RTL architecture/development/verification, strong SystemVerilog or VHDL skills, experience with Microship Polarfire/AMD Zynq/Versal/Ultrascale, verification methodologies, Git, Python/Tcl/Bash, C/C++ on Linux, and eligibility for DoD security clearance.
SystemVerilog, VHDL, Microship Polarfire, AMD Zynq US+, Versal, AMD Ultrascale, Vivado, Mentor Modelsim/Questasim, AXI, PCIe, DDR4, DDR5, JESD204B, JESD204C, 100Gb ethernet, SPI, I2C, UART, CAN FD, LVDS, Git, Python, Tcl, Bash, Linux, C/C++
3mo
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Senior/Principal FPGA Design Engineer
Calabasas or Burnaby or Austin
$139k-$232k/yr RemoteFull Time
8+ YOE8+ years FPGA design experience; BSc/MSc in EE or CE; strong VHDL/SystemVerilog; knowledge of Ethernet, SerDes, DDR5; leadership and mentoring skills.
VHDL, SystemVerilog, Tcl, Perl, Python, Ethernet, PCIe, Interlaken, DDR5, RLDRAM3, SerDes
1mo
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Principal FPGA / RTL Design Engineer - Signal Processing
Los Angeles or Irvine
$175k-$225k/yr HybridFull Time
10+ YOEBS in ECE/CS or related; 10+ yrs RTL/FPGA design or 6+ yrs with PhD; Xilinx FPGAs, Vivado; fixed-point DSP; US person.
Xilinx FPGAs, Vivado IDE, Fixed-point arithmetic, Digital Signal Processing, MATLAB, Python, Perl
1mo
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Spacecraft Field Programmable Gate Array (FPGA) Engineer - Millennium Space Systems
El Segundo, California, United States
$83k-$123k/yr OnsiteFull Time
2+ YOEBachelor's in engineering or related STEM, 2+ years FPGA experience, Verilog/System Verilog, ability to obtain U.S. Secret clearance (U.S. citizenship), experience with Xilinx/AMD devices and serial/high-speed protocols preferred.
Verilog, System Verilog, Xilinx, AMD, Microchip, Microsemi, SPI, I2C, UART, SpaceWire, Gigabit Ethernet, PCIe, 802.11, oscilloscopes, logic analyzers, serial protocol analyzers, Python, Tcl, Bash, Linux, C/C++, UVM, formal methods
1mo
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FPGA Verification Engineer II
El Segundo, California, United States
$118k-$142k/yr OnsiteFull Time
2+ YOEBS/MS in CS/EE/CE, 2+ years verification and automation experience, proficiency with VHDL/Verilog/SystemVerilog, UVM/UVMf, DPI-C, TLM, QEMU, VIP, Linux, MATLAB/Python, and Xilinx tools; CI and regression experience.
VHDL, Verilog, SystemVerilog, C, C++, SystemC, UVM, UVMf, DPI-C, TLM, Formal CDC, QEMU, QEMU-RP, VIP, MATLAB, Python, Linux, Xilinx
1w
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FPGA Digital Design Engineer Level 3/4 (AHT)
Northridge, California, United States
$125k-$188k/yr OnsiteFull Time
5+ YOEBachelor's in engineering or STEM, 5+ years digital design experience (or 3+ with MS), hands-on VHDL/Verilog FPGA design, EDA tool experience, ability to obtain US Secret clearance.
VHDL, Verilog, Vivado, Quartus, QuestaSim, MATLAB, SimuLink, Modelsim, VxWorks, AXI, DMA, PCIe, HSSI, DDR3, Ethernet
2mo
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ASIC/FPGA Verification Engineer - (Associate, Experienced, or Lead) - SoCal
El Segundo or Huntington Beach
OnsiteFull Time
5+ YOEBachelor's degree in engineering or related field; experience in ASIC/FPGA verification; SystemVerilog/UVM; HDL proficiency; testbenches, coverage models, and regression testing experience.
SystemVerilog, UVM, HDL, Verilog, Python, Make, Perl, Git, SV Assertions
1w
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FPGA Verification Engineer, Air Dominance and Strike (Fastwater Staffing)
Costa Mesa, California, United States
RemoteFull Time
2+ YOEBachelor's in EE/CE, 2+ years FPGA/ASIC verification, proficient in SystemVerilog/UVM/SVA, experience with industry simulators, Git and Linux, eligible for U.S. Secret clearance.
SystemVerilog, UVM, SVA, Questa, VCS, Xcelium, Vivado, Git, Linux, SVUnit, Python, Tcl, Makefile, Nix
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