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105 design verification engineer jobs at 37 companies in Compton, CA

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Design Verification Engineer
Los Angeles or San Diego
OnsiteFull Time
Apple
AppleNASDAQ: AAPL: Designs and sells consumer electronics, software, and online services.
3+ YOEBachelor's degree required; 3+ years in hardware verification preferred; SystemVerilog/UVM expertise; test-benches, DV methodology, and verification environments; experience with PCIe/USB, DDR protocols; scripting in Python/Perl/TCL; C/C++ knowledge.
SystemVerilog, UVM, Simulators, Waveform Viewers, Python, Perl, TCL, C/C++
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Design Verification Engineer - Early Career
Santa Clara or Irvine
$87k-$130k/yr OnsiteFull Time
Marvell
MarvellNASDAQ: MRVL: Designs and develops high-performance semiconductor and infrastructure solutions.
1+ YOEBachelor’s or Master’s in Electrical/Computer Engineering with 1–3 years experience; Verilog/VHDL; Linux and Python; PCB/architecture knowledge; experience with UVM and ASIC verification.
Verilog, VHDL, UVM, Synopsys, Cadence, Mentor Graphics, Linux, Python, PCIe, Memory Architecture
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ASIC Design Verification Engineer
Irvine or Andover or Broomfield
$129k-$207k/yr OnsiteFull Time
Broadcom
BroadcomNASDAQ: AVGO: Designs and sells semiconductors and infrastructure software to enterprises.
3+ YOEConstrained-random design verification experience using System Verilog/UVM, coverage-driven methodologies, experience with VCS/Incisive and scripting (Python/Perl). Degree with significant related experience required (varies by degree).
System Verilog, UVM, VCS, Incisive, Python, Perl
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Principal Design Verification Engineer (Silicon Engineering)
Sunnyvale or Austin or Irvine or Redmond
$210k-$310k/yr OnsiteFull Time
SpaceX
SpaceX: Designs and launches advanced rockets and satellite internet constellations.
10+ YOEBachelor’s in electrical/computer engineering or computer science; 10+ years in design verification and test bench development.
UVM, OVM, VMM, Python, RTL
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ASIC Design Verification Engineer
Los Angeles or United States
$130k-$200k/yr OnsiteFull Time
K2 Space
K2 Space: Develops high-power satellite platforms for heavy-lift launch vehicles.
3+ YOEB.S./M.S. in EE/CE or related, 3+ years ASIC/SoC verification experience, SystemVerilog/UVM/SVA, simulation and waveform tools (VCS, Xcelium, Questa, Verdi, SimVision), scripting (Python/Perl/TCL), and Git.
SystemVerilog, UVM, SystemVerilog Assertions (SVA), VCS, Xcelium, Questa, Verdi, SimVision, Python, Perl, TCL, Git, APB, AHB, AXI
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Senior ASIC Design Verification Engineer - Terawave
Los Angeles or Seattle or California or Washington or Texas or United States
$230k-$323k/yr RemoteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
8+ YOEBS/MS in EE/CE, 8+ years ASIC/SoC verification experience, deep System Verilog and UVM expertise, verification planning, coverage closure, RTL/debugging, cross-functional collaboration.
System Verilog, UVM, RTL
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Associate ASIC/FPGA Design or Verification Engineer
El Segundo or Huntington Beach or Fairfax
$99k-$133k/yr OnsiteFull Time
Boeing
BoeingNYSE: BA: Designing and manufacturing commercial aircraft and defense systems.
2+ YOEUS citizenship and ability to obtain U.S. Secret clearance; BS in engineering or related field; experience with ASIC/FPGA design or verification and HDL (Verilog/VHDL/System Verilog); familiarity with verification methodologies and scripting.
Verilog, VHDL, System Verilog, System Verilog Assertions, UVM, Palladium, Make, Perl, Python, svn, cvs, git, Linux, JESD204C, PCIe, Ethernet
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Sr. Satellite Design Verification Engineer, Amazon Leo
Irvine or Austin or Sunnyvale or Redmond or San Diego
OnsiteFull Time
Amazon
AmazonNASDAQ: AMZN: Global online retail and cloud computing technology provider.
7+ YOEBachelor's in Electrical/Communications Engineering; 3+ years UVM/SystemC/DPI-C; 7+ years verification in communications; preferred advanced degree; Matlab familiarity; DV/integration experience.
UVM, C, SystemC, DPI-C, Matlab
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Lead Verification & Validation Engineer
Palo Alto or Irvine
$130k-$155k/yr OnsiteFull Time
ALTEN
ALTENEuronext Paris: ATE: Provides engineering and technology consulting services to industrial clients.
5+ YOELead V&V strategy, mentor engineers, design/test automation, and oversee automotive software/system validation.
CAN, LIN, Ethernet, FlexRay, dSPACE, Vector VT, DBC, LDF, ARXML, HIL, MATLAB, Python, C/C++, Automotive testing tools
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Principal Design Engineer CMOS Design Engineer – RF / Mixed-Signal
Manhattan Beach, California, United States
$114k-$171k/yr OnsiteFull Time
Northrop Grumman
Northrop GrummanNYSE: NOC: Designs and manufactures advanced aerospace and defense systems.
5+ YOETransistor-level CMOS RF/mixed-signal IC design experience, SPICE and Cadence proficiency, PVT and Monte Carlo verification, degree in electrical engineering (B.S. with 5+ years or advanced degree with reduced experience), strong communication skills.
Cadence Virtuoso, SPICE, spectrum analyzer, oscilloscope, probe station, VNAs
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Sr. Principal AMS Verification Engineer (Irvine, CA, US)
Irvine, California, United States
$143k-$286k/yr OnsiteFull Time
Skyworks Solutions
Skyworks SolutionsNASDAQ: SWKS: Designs and manufactures analog and mixed-signal semiconductor solutions.
8+ YOERequires BS+15 yrs (MS+12 or PhD+8) experience; strong AMS design/verification background, Verilog-A and SystemVerilog RNM modeling, Cadence Virtuoso/ADS experience, Python scripting, leadership and communication skills.
Cadence Virtuoso, ADS, Verilog-A, SystemVerilog, SystemVerilog Real Number Modeling (RNM), Python
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Associate ASIC/FPGA Design or Verification Engineer
El Segundo or Huntington Beach or Fairfax
$99k-$133k/yr OnsiteFull Time
Boeing
BoeingNYSE: BA: Designs and manufactures aircraft, defense systems, and space technology.
2+ YOEUS citizenship with ability to obtain U.S. Secret clearance, Bachelor\u0000s degree in a relevant field, experience with ASIC/FPGA design or verification, and RTL experience with Verilog/VHDL/SystemVerilog.
Verilog, VHDL, SystemVerilog, System Verilog Assertions, UVM, Palladium, Make, Perl, Python, svn, cvs, git, Linux, ARM, JESD204C, PCIe, Ethernet
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Principal Design Engineer CMOS Design Engineer – RF / Mixed-Signal
Manhattan Beach, California, United States
$114k-$171k/yr OnsiteFull Time
Northrop Grumman
Northrop GrummanNYSE: NOC: Develops and manufactures advanced aerospace, defense, and space systems.
5+ YOEBachelor's in EE (or related) with 5+ years (masters 3+, PhD 0–2); transistor-level CMOS RF/mixed-signal design experience; SPICE and Cadence proficiency; PVT/Monte Carlo verification; strong communication.
Cadence Virtuoso, SPICE, VNA, spectrum analyzer, oscilloscope, probe station
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ASIC/FPGA Verification Engineer - (Associate, Experienced, or Lead) - SoCal
El Segundo or Huntington Beach
$86k-$171k/yr OnsiteFull Time
Boeing
BoeingNYSE: BA: Designs and manufactures commercial airplanes, defense systems, and space technology.
2+ YOEBachelor's degree or equivalent, ASIC/FPGA verification experience using SystemVerilog/UVM, coverage and regression development, testbench design, revision control (svn/cvs/git), and Linux proficiency.
UVM, SystemVerilog, SystemVerilog Assertions, svn, cvs, git, Linux, Palladium, Make, Perl, Python, JESD204C, PCIe, Ethernet
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Physical Design Engineer
San Jose or Irvine
$150k-$250k/yr OnsiteFull Time
Celero Communications
Celero Communications: Developing high-performance coherent DSP technology for AI connectivity.
5+ YOEBachelor's/Master's in EE, 5+ years full-chip physical verification experience, multiple tapeouts, hands-on with ICV or Calibre, ability to assemble PV flow and floorplanning expertise; Tcl/Python/shell automation preferred.
ICV, Calibre, Tcl, Python, Shell
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Hardware Verification Engineer (Agoura Hills, CA, US)
Agoura Hills, California, United States
$141k-$226k/yr OnsiteFull Time
Teradyne
TeradyneNASDAQ: TER: Designs and manufactures automated test equipment and advanced robotics systems.
Strong experience with schematic capture, PCB layout, hardware bring-up, design and debug of complex high-component-count boards, high-current power and mixed-signal electronics, production/DFM support, and independent end-to-end problem solving.
ATE
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Design Quality Engineer
Irvine, California, United States
$105k-$135k/yr OnsiteFull Time
TAE Technologies
TAE Technologies: Developing commercial fusion power for clean, carbon-free energy.
5+ YOEBS in technical or life science,5+ years in medical device quality systems (ISO 13485,21 CFR 820),strong technical writing,test planning,verification/validation experience,MS Office proficiency,and ability to travel up to 90 days/yr.
Microsoft Office
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Staff FPGA Design Engineer
Irvine, California, United States
$150k-$190k/yr OnsiteFull Time
Terran Orbital
Terran OrbitalNYSE: LMT: Manufactures modular spacecraft for aerospace and defense missions.
8+ YOEBachelor's in EE/CE, 8+ years FPGA RTL architecture/development/verification, strong SystemVerilog or VHDL skills, experience with Microship Polarfire/AMD Zynq/Versal/Ultrascale, verification methodologies, Git, Python/Tcl/Bash, C/C++ on Linux, and eligibility for DoD security clearance.
SystemVerilog, VHDL, Microship Polarfire, AMD Zynq US+, Versal, AMD Ultrascale, Vivado, Mentor Modelsim/Questasim, AXI, PCIe, DDR4, DDR5, JESD204B, JESD204C, 100Gb ethernet, SPI, I2C, UART, CAN FD, LVDS, Git, Python, Tcl, Bash, Linux, C/C++
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Principal Engineer Pre-Silicon Digital Verification
Andover or Austin or El Segundo
$146k-$201k/yr OnsiteFull Time
Infineon Technologies
Infineon TechnologiesFrankfurt Stock Exchange: IFX: Designs and manufactures semiconductors for power and IoT systems.
Expertise in ASIC design and digital/mixed-signal verification, System Verilog and UVM, scripting (Unix/Linux shell, Perl, Python), testbench and coverage development, formal verification and analog behavioral modeling.
System Verilog, UVM, Unix/Linux shell, Perl, Python
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Director of Verification & Validation
Huntington Beach, California, United States
$180k-$230k/yr OnsiteFull Time
BiVACOR
BiVACOR: Developing an advanced total artificial heart for patients.
8+ YOEBachelor's in Biomedical or Mechanical Engineering, 8+ years Class III medical device V&V, knowledge of FDA and IEC/ISO standards, design control expertise, strong technical writing, and experience leading V&V teams.
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