29 ic design jobs at 12 companies in Glendale, AZ
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Principal Power IC Design Engineer
Chandler, Arizona, United States
OnsiteFull Time
8+ YOEMSEE (10+ yrs) or PhD (8+ yrs) power IC design experience; transistor-level design of power management circuits; experience with BCD/HV-CMOS, control-loop design; proficiency with Cadence Virtuoso and Spectre/APS; leadership from concept to silicon.
Cadence Virtuoso, Spectre/APS
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Senior Technical Staff Engineer – IC Analog Design
Chandler, Arizona, United States
OnsiteFull Time
12+ YOESenior IC analog design engineer with 12+ years, DAC/ADC expertise, CMOS design, lab testing, Cadence tools, scripting.
Cadence Virtuoso, Cadence Spectre, MATLAB, Python, Tcl
1mo
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Senior Design Lead (122083)
Chandler or Hillsboro
OnsiteContract
10+ YOEBachelor's or Master's in Electrical/Electronics Engineering; ~10+ years IC packaging/package design for senior level (4–6+ years mid); hands-on experience with Siemens (Mentor) Xpedition or Cadence Allegro/APD, physical/substrate design, SI/PI-aware design, DFM and design rule compliance.
Siemens (Mentor) Xpedition (XPD), Cadence Allegro, Advanced Package Designer (APD / SiP)
3w
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Staff Analog Design Engineer
Chandler, Arizona, United States
HybridFull Time
8+ YOETypically 8+ years analog/mixed-signal IC design experience; Bachelor's in electrical/electronics engineering; strong technical leadership, mentoring, circuit design, simulation, verification, lab evaluation, and customer-facing skills.
1mo
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Manager, Analog Design Engineering
Phoenix, Arizona, United States
OnsiteFull Time
20+ YOEBSEE or MSEE and 20+ years experience in precision analog/mixed-signal IC design, transistor-level and low-power design, ability to translate system requirements, product development experience, and strong communication and leadership skills.
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Analog Design Engineer
Scottsdale or Chandler or Phoenix
$134k-$168k/yr OnsiteFull Time
10+ YOEBachelor's in Electronic Engineering, 10+ years analog IC design experience, proficiency with Cadence Virtuoso and Mentor Graphics, EM/ESD awareness, bench testing skills, scripting (SKILL/Perl/Python/TCL) a plus, strong communication.
Cadence Virtuoso, Mentor Graphics, SKILL, Perl, Python, TCL
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Sr Digital Design Engineer
Chandler, Arizona, United States
OnsiteFull Time
10+ YOEM.S. in electrical, computer, or related engineering; 10+ years in digital IC design; Verilog/SystemVerilog, EDA tools, synthesis, timing analysis, verification, UVM, and technical leadership experience.
Verilog, SystemVerilog, UVM, Cadence, Synopsys, Siemens EDA
3mo
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Sr. MTS, Power Module Design
Scottsdale or San Jose
OnsiteFull Time
onsemi: Designs and manufactures semiconductor solutions for power and sensing.
15+ YOEMasters in Electrical/Electronic/Mechatronics or related field; 15+ years in power semiconductors/electronics; 5+ years in power module design; ECAD/MCAD tools; strong leadership; English fluent; director-equivalent IC role.
ECAD (PSpice, SIMetrix, Ansys EM, Ansys CFD), MCAD (SolidWorks, PTC Creo), Power Semiconductors, Power Module Design
3d
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Senior Principal Mixed Signal Design Engineer (Hybrid)
Goleta or Phoenix
$146k-$277k/yr HybridFull Time
10+ YOESTEM degree with 10+ years of relevant experience or advanced degree with 7+ years; requires mixed-signal ASIC/ROIC, CMOS IC design, semiconductor processing, simulation, layout, testing, and team leadership experience.
Cadence, Mentor Graphics, MATLAB, Python, UNIX, SystemVerilog, Verilog-AMS, Conformal, Innovus, RTL
2d
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Package Layout Design Engineer , Annapurna Labs - AI Silicon Packaging
Tempe or Austin or Cupertino
$136k-$213k/yr OnsiteFull Time
5+ YOEBachelor's degree in electrical engineering or related field and 5+ years of IC package layout and physical design experience. Requires package layout tools, advanced packaging, DFM, and physical verification expertise.
Cadence APD/SiP, Synopsys IC Packaging, Mentor Xpedition, Python, Perl, ARM, TCL, Skill, Ravel, DRC
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Design Technology Tool Enablement Engineer
Hillsboro or Santa Clara or Phoenix
$174k-$285k/yr HybridFull Time
8+ YOEMaster's or PhD in a STEM field; 8+ years or 5+ years with PhD; strong Python/Tcl/Perl scripting; experience with EDA tools; semiconductor process knowledge.
Python, Tcl, Perl, Calibre, ICV, Pegasus, SVRF/TVF, PXL, PVL
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Analog Mixed Signal Modeling Engineer (UL - 02)
Austin or Chandler or Greensboro
HybridFull Time
Master's in EE/Computer Eng required. Experience in mixed-signal product development, analog IC design, SystemVerilog RNM, AMS simulators, verification methodologies, and strong analytical and communication skills.
SystemVerilog Real Number Modeling (SV-RNM), Verilog AMS, AMS simulators, System Verilog Assertions, PSL Assertions, Perforce, GIT, UVM, Simulink, Simscape, Python
1mo
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R&D Engineer Hardware 4
Chandler, Arizona, United States
$110k-$176k/yr OnsiteFull Time
6+ YOEMSEE or PhD preferred, 6+ years industry experience, expertise in mixed-signal/analog IC design, Cadence Virtuoso, SPICE simulators, Verilog, Synopsys Liberty, Python; silicon validation and documentation experience.
Cadence Virtuoso, ADE, Spectre, Hspice, Finesim, Verilog, Synopsys Liberty, Python
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