1mo
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Principal Power IC Design Engineer
Chandler, Arizona, United States
OnsiteFull Time
8+ YOEMSEE (10+ yrs) or PhD (8+ yrs) power IC design experience; transistor-level design of power management circuits; experience with BCD/HV-CMOS, control-loop design; proficiency with Cadence Virtuoso and Spectre/APS; leadership from concept to silicon.
Cadence Virtuoso, Spectre/APS
2mo
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Senior Technical Staff Engineer – IC Analog Design
Chandler, Arizona, United States
OnsiteFull Time
12+ YOESenior IC analog design engineer with 12+ years, DAC/ADC expertise, CMOS design, lab testing, Cadence tools, scripting.
Cadence Virtuoso, Cadence Spectre, MATLAB, Python, Tcl
1mo
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Senior Design Lead (122083)
Chandler or Hillsboro
OnsiteContract
10+ YOEBachelor's or Master's in Electrical/Electronics Engineering; ~10+ years IC packaging/package design for senior level (4–6+ years mid); hands-on experience with Siemens (Mentor) Xpedition or Cadence Allegro/APD, physical/substrate design, SI/PI-aware design, DFM and design rule compliance.
Siemens (Mentor) Xpedition (XPD), Cadence Allegro, Advanced Package Designer (APD / SiP)
3w
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Physical Design Engineer
Massachusetts or Phoenix
$91k-$149k/yr OnsiteFull Time
0+ YOEDesign and implement physical IC/SoC from RTL to GDS, perform synthesis/place-and-route/CTS/STA, power and noise analysis, verification and optimization using EDA tools.
EDA tools, TCL
2w
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Staff Analog Design Engineer
Chandler, Arizona, United States
HybridFull Time
8+ YOETypically 8+ years analog/mixed-signal IC design experience; Bachelor's in electrical/electronics engineering; strong technical leadership, mentoring, circuit design, simulation, verification, lab evaluation, and customer-facing skills.
3w
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Manager, Analog Design Engineering
Phoenix, Arizona, United States
OnsiteFull Time
20+ YOEBSEE or MSEE and 20+ years experience in precision analog/mixed-signal IC design, transistor-level and low-power design, ability to translate system requirements, product development experience, and strong communication and leadership skills.
1mo
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Analog Design Engineer
Scottsdale or Chandler or Phoenix
$134k-$168k/yr OnsiteFull Time
10+ YOEBachelor's in Electronic Engineering, 10+ years analog IC design experience, proficiency with Cadence Virtuoso and Mentor Graphics, EM/ESD awareness, bench testing skills, scripting (SKILL/Perl/Python/TCL) a plus, strong communication.
Cadence Virtuoso, Mentor Graphics, SKILL, Perl, Python, TCL
2mo
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Senior Manager, Design Engineering
Waddell, Arizona, United States
OnsiteFull Time
8+ YOE3+ MgmtOversee design, development, and manufacturing of three-phase transformers; lead managers and senior ICs; onsite in Waddell, AZ; BS in engineering; 8+ years in transformer design; familiar with IEEE/IEC/DOE standards.
2mo
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MTS, Power Module Design
Munich or Scottsdale
HybridFull Time
onsemi: Designs and manufactures semiconductor solutions for power and sensing.
12+ YOEMasters in electrical/electronic/mechatronics engineering; 12+ years in power semiconductors/modules; ECAD/MCAD tools; English fluency; senior IC-level individual contributor.
PSpice, SIMetrix, Ansys EM, Ansys CFD, Solidworks, PTC Creo
2mo
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High Speed Analog Design Engineer
Chandler, Arizona, United States
OnsiteFull Time
3+ YOEMS in Electrical Engineering with 3–5 years IC development experience, or PhD with 1–2 years experience; high-speed analog/mixed-signal design; Cadence tools; MATLAB/Simulink; strong SI/jitter/noise knowledge; English fluency.
Cadence Virtuoso, Cadence Spectre, MATLAB, Simulink
1mo
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Analog Mixed Signal Modeling Engineer (UL - 02)
Austin or Chandler or Greensboro
HybridFull Time
Master's in EE/Computer Eng required. Experience in mixed-signal product development, analog IC design, SystemVerilog RNM, AMS simulators, verification methodologies, and strong analytical and communication skills.
SystemVerilog Real Number Modeling (SV-RNM), Verilog AMS, AMS simulators, System Verilog Assertions, PSL Assertions, Perforce, GIT, UVM, Simulink, Simscape, Python
2w
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R&D Engineer Hardware 4
Chandler, Arizona, United States
$110k-$176k/yr OnsiteFull Time
6+ YOEMSEE or PhD preferred, 6+ years industry experience, expertise in mixed-signal/analog IC design, Cadence Virtuoso, SPICE simulators, Verilog, Synopsys Liberty, Python; silicon validation and documentation experience.
Cadence Virtuoso, ADE, Spectre, Hspice, Finesim, Verilog, Synopsys Liberty, Python
4w
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Sr. Package Layout Engineer, Annapurna Labs - AI Silicon Packaging
Tempe or Austin or Cupertino
$159k-$248k/yr OnsiteFull Time
10+ YOEBachelor's in EE or related, 10+ years IC package layout and physical design experience, expertise with advanced packaging (2.5D/3D, WLP, RDL, TSV), package DRC/DFM, and collaboration with SI/PI and manufacturing teams.
Cadence APD/SiP, Synopsys IC Packaging, Mentor Xpedition, Python, TCL, Skill, Ravel
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