55 ic design jobs at 21 companies in Pflugerville, TX
3mo
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IC Package Design Engineer
Los Angeles or San Francisco or Austin
OnsiteFull Time
Bachelor's degree; IC package physical design experience; Cadence Allegro/Mentor Xpedition; SiP/PoP knowledge; high-speed and SI/PI; DRC/DFM; automation scripting.
Cadence Allegro, Mentor Xpedition, Calibre, CAM350, HFSS, PowerSI
2mo
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Sr. IC Package Design Engineer (Silicon Engineering)
Austin or Irvine
OnsiteFull Time
5+ YOEBachelor's degree in electrical/computer engineering or physics; 5+ years IC package design experience; strong SI/PI, RF, and CAD tool proficiency.
Cadence APD+/SIP, SIWave, HFSS, ADS, Package design tools
1w
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R&D Engineer IC Design 4
Austin or San Jose
$122k-$195k/yr OnsiteFull Time
6+ YOEDesign and verify RTL/Verilog blocks for ASICs including synthesis, timing closure, formal verification, scripting, and RTL/gate-level power analysis. BS/MS in ECE and 6+ years experience.
Verilog, RTL, TCL, Perl, Synopsys Design Compiler, DC topo, Cadence RTL Compiler, Primetime, liberty (LIB), Synopsys Formality, Cadence Conformal, Spyglass, svn, git
15h
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3D-IC Application Engineer
Austin or Boulder or Fremont or San Diego or Santa Clara or Wilsonville
$125k-$251k/yr HybridFull Time
4+ YOEMSEE/BSEE and 4+ years of design experience, advanced IC package or interposer layout expertise, package design tools, scripting, Windows/Linux, and customer-facing applications engineering skills.
Innovator 3D IC Layout, Innovator3D IC Integrator, Xpedition, Calibre, HyperLynx, Cadence APD/SiP, Siemens Xpedition/i3DL, Siemens XSI/i3DI, Cadence OrbitIO/ISP, Synopsys 3DIC Compiler, Microsoft Excel, TSMC InFO, CoWoS, Intel EMIB, Foveros, ASE FoCUS, Amkor SWIFT, Samsung I/H/X-Cube, Verilog, LEF/DEF, GDS, OASIS, Sigrity, SIWave, ADS, Siemens Calibre DRC, Siemens Calibre LVS, 3DSTACK, Microsoft Word, Microsoft PowerPoint, VBS, Python, Tcl, Perl, Windows, Linux
1w
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Senior IC Package Design Engineer - TeraWave
San Diego or Austin or California
$230k-$323k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
7+ YOEBachelor's in EE or related,7+ years industry experience delivering IC packaging,expertise with HFSS/EMX/Momentum,Cadence Allegro experience preferred,RF/mmWave and power/signal integrity expertise,U.S. work authorization required.
HFSS, EMX, Momentum, Cadence Allegro
2mo
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Mixed Signal IC Layout Designer (RS-50022405)
Austin, Texas, United States
OnsiteFull Time
10+ YOEAssociates Degree in Electronic/IC layout CAD; 10+ years IC layout; analog/mixed-signal layouts; Cadence Virtuoso XL; Mentor Calibre; floor planning.
Cadence Virtuoso XL, Mentor Calibre, layout CAD tools, foundry PDKs
2mo
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Analog Design Engineer
Austin, Texas, United States
$317k/yr OnsiteFull Time
10+ YOE10+ years analog/mixed-signal IC design; MS or PhD in Electrical Engineering; 25 Gbps SerDes experience; Cadence tools; post-silicon bring-up; collaborative team player.
Cadence Virtuoso, Cadence Spectre, Verilog-A, EM-IR, Monte Carlo, Post-silicon test equipment
2mo
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CPU Physical Design Engineer
Austin, Texas, United States
$106k-$173k/yr OnsiteFull Time
2+ YOEBS in CE/EE with 2+ years or MS with 1+ years; 1+ year in synthesis; IC design tools; DRC/LVS; TCL scripting.
Synopsys, Cadence, Synthesis tools, Place and Route, Static Timing Analysis, DRC/LVS, TCL Scripting
2mo
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Senior Analog Design Engineer
Austin, Texas, United States
$125k-$231k/yr HybridFull Time
3+ YOEMS in Electrical Engineering or equivalent with 3+ years analog/mixed-signal IC design; strong CAD, UNIX, MATLAB skills; good communication and leadership potential.
UNIX, MATLAB, Cadence (CAD tools), Verilog, VerilogA, Scripting (Tcl, Perl, SKILL)
11h
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3D-IC Application Engineer
Austin or Boulder or Fremont or San Diego or Santa Clara or Wilsonville
$125k-$251k/yr HybridFull Time
4+ YOEMSEE/BSEE and 4+ years of design experience with advanced IC package or interposer layout. Requires package design tools, scripting, Windows/Linux, and strong presentation and customer skills.
Innovator 3D IC Layout, Innovator3D IC Integrator, Xpedition, Calibre, HyperLynx, Cadence APD/SiP, Siemens XSI/i3DI, Cadence OrbitIO/ISP, Synopsys 3DIC Compiler, Microsoft Excel, TSMC InFO, CoWoS, Intel EMIB, Foveros, ASE FoCUS, Amkor SWIFT, Samsung I/H/X-Cube, Verilog, LEF/DEF, GDS, OASIS, Sigrity, SIWave, ADS, Microsoft Word, Microsoft PowerPoint, VBS, Python, Tcl, Perl, Windows, Linux
2mo
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Analog Design Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOE5+ years designing advanced analog/mixed-signal ICs (PLLs, ADCs/DACs, SerDes, timing circuits) with FinFET/GAA process experience; B.Sc/M.Sc in EE/CE; tape-out, layout understanding, verification, and teamwork skills.
4d
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Senior Principal RF Design Engineer
Austin or Burlington or Cary
OnsiteFull Time
10+ YOEExpertise in mmWave RF IC design (30+ GHz), PA/LNA/mixer/VCO and PLL design, EM and thermal modeling, lab validation experience; usually M.Sc./Ph.D.; 10+ years industry experience.
VSS, Cadence Virtuoso, VRF, EMX, Clarity, Layout MXL, QRC, Pegasus, spectrum analyzer, VNA, probe station
1mo
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Staff Digital Design Engineer – SOC Low Power, Clocking & Integration
Austin, Texas, United States
$143k-$266k/yr HybridFull Time
10+ YOEBS/MS in Electrical Engineering, 10+ years digital CMOS IC design experience, expertise in Verilog/System Verilog, UPF/CPF, AXI/AHB/APB, RTL design, synthesis, timing, power analysis, simulation, scripting (Python/Perl/Tcl), and leading small teams.
Verilog, System Verilog, UPF, CPF, AXI, AHB, APB, RISC-V, C, Python, Perl, Tcl, Perforce, Git, Methodics
2mo
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Physical Design Verification Manager, Annapurna Labs
Cupertino or Austin
$175k-$272k/yr OnsiteFull Time
10+ YOE5+ MgmtBS/MS in EE/CS plus extensive PDV experience; leadership, Calibre/IC Validator/PVS, scripting, and team management.
Calibre, IC Validator, PVS, Python, Perl, Tcl
2mo
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Design & Verification Engineer, Analog Power Management (7682) (Austin, TX, US)
Austin, Texas, United States
$120k-$170k/yr OnsiteFull Time
7+ YOEMSEE with 7+ years in hands-on power management design/verification; SIMPLIS knowledge; PCB design/layout in PM; IC design/packaging familiarity; strong teamwork; power delivery modeling
SIMPLIS, PCB Design, Power Delivery Modeling
3mo
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Full-Chip Physical Design Verification Engineer
Austin or Fort Collins or Santa Clara
$100k-$500k/yr HybridFull Time
7+ YOE7–14 years of hands-on CPU/IP/SoC physical verification experience; strong DRC/LVS/ERC/DFM tooling skills; scripting in Python and TCL.
Calibre, ICV, Pegasus, FC, Innovus, Python, TCL
1mo
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PMTS, A&D Field Application Eng
Austin or Santa Clara or Richardson or Malta
$145k-$236k/yr OnsiteFull Time
15+ YOEBachelor's degree in electrical engineering (or equivalent), extensive semiconductor IC design/tapeout/process experience, eligible for U.S. Secret clearance, strong IC design flow and EDA tool knowledge, customer engagement and program management skills.
EDA
2mo
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Senior Analog Engineering Manager
Austin, Texas, United States
OnsiteFull Time
12+ YOE5+ MgmtLead DDR5/DDR6 PHY design and team; 12+ years analog/mixed-signal IC design; 5+ years people management; strong leadership, architecture and delivery.
DDR5, DDR6, AnalogDesign, MixedSignalIC, HighSpeedIO, Clocking, Verification, SiliconDebug
4w
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MTS Field Application Eng - RF & Photonics
Santa Clara or Richardson or Austin
$99k-$161k/yr OnsiteFull Time
10+ YOEBachelor's in electrical engineering or equivalent, 10+ years semiconductor design/tapeout/process experience, knowledge of IC design flows and EDA tools, strong communication and program management skills.
EDA tools
3w
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Principal PCIe Subsystem RTL lead
San Jose or Santa Clara or Austin or Seattle or Boston
HybridFull Time
10+ YOE10+ years digital IC design experience with 4+ years PCIe subsystem design/integration, strong SystemVerilog RTL skills, experience integrating PCIe controller/SerDes PHY, multi-clock-domain design, and ability to lead architectural work.
SystemVerilog, UVM, PCIe, CXL, SerDes
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