171 layout jobs at 97 companies in Hercules, CA
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Layout Engineer - Labs
San Francisco, California, United States
$212k-$312k/yr OnsiteFull Time
8+ YOE8+ years PCB layout experience, expert Altium Designer skills, strong signal/power integrity and mixed-signal layout knowledge, DFM/IPC familiarity, and cross-functional collaboration on flight-grade hardware.
Altium Designer, SolidWorks, Creo, Gerber, ODB++
2w
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RFIC Layout Designer (RFIC Engineering)
Redmond or Irvine or Palo Alto
OnsiteFull Time
1+ YOEIC layout experience for RF/analog designs, 1+ years professional layout or 3+ years without degree; skills in analog/RF layout, advanced-node processes, scripting, revision control, and Linux; ITAR eligibility required.
Skill, shell scripting, Perl, Python, Linux, GDS
1mo
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Senior PCB Layout Engineer
Sunnyvale, California, United States
$106k-$214k/yr OnsiteFull Time
8+ YOE8+ years PCB layout experience, expert in Cadence Allegro, high-speed design, SI/PI and impedance control, HDI and manufacturing knowledge, ability to lead layout planning and mentor junior designers.
Cadence Allegro PCB Designer, Cadence Allegro, Constraint Manager, SKILL, ODB++, IPC-2581, Gerber
1d
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Senior Package Layout Engineer - Hardware
Santa Clara or Nevada or Washington or Arizona or Oregon or California
$136k-$259k/yr HybridFull Time
5+ YOEBachelor's degree in electrical engineering or equivalent experience, 5+ years of PCB layout experience, and expertise with Cadence APD or SiP, high-speed design, substrate layout, and PCB layout tools.
Cadence APD, SiP, Constraint Manager, Virtuoso, Calibre, Valor, CAD
22h
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PCB Layout Engineer
Mountain View, California, United States
$200k-$275k/yr OnsiteFull Time
8+ YOERequires 8+ years of complex high-speed, high-current PCB layout experience, constraint-driven design expertise, and hands-on experience with Cadence Allegro, Siemens Xpedition, Altium, or equivalent tools.
Cadence Allegro, Siemens Xpedition, Altium, Gerber, ODB++, IPC-2581, CoWoS, EMIB, HBM, IPC CID, IPC CID+
1mo
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PCB Layout Engineer
San Carlos, California, United States
$128k-$160k/yr OnsiteFull Time
1+ YOEBachelor's in EE/CompE/Physics or related, 1+ years PCB layout experience for multilayer/high-speed designs, familiarity with signal/power/thermal/EMI considerations, and experience with PCB design tools and manufacturability.
Altium Designer, Cadence Allegro, Mentor Graphics
1d
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Senior Package Layout Engineer - Hardware
Santa Clara or Nevada or Oregon or Arizona or Washington or California
$136k-$259k/yr HybridFull Time
5+ YOEBachelor's degree in electrical engineering or equivalent experience; 5+ years in PCB layout; substrate layout, Cadence APD or SiP, high-speed signal integrity, and related CAD tools required or preferred.
Cadence APD, SiP, Constraint Manager, Virtuoso, Calibre, Valor
1mo
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Senior PCB Layout Engineer
Sunnyvale, California, United States
$106k-$214k/yr OnsiteFull Time
8+ YOE8+ years PCB layout experience; expert in Cadence Allegro and Constraint Manager; strong high-speed design, SI/PI, HDI, impedance control, and PCB manufacturing knowledge.
Cadence Design Systems, Cadence Allegro PCB Designer, Cadence Allegro, Constraint Manager, SKILL, ODB++, IPC-2581, Gerber
1mo
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Senior PCB Layout Engineer
Sunnyvale, California, United States
$106k-$214k/yr OnsiteFull Time
8+ YOE8+ years PCB layout experience with expert Cadence Allegro proficiency, high-speed design, impedance/stackup planning, HDI, EMI/EMC, PCB fabrication knowledge, and mentoring experience.
Cadence Design Systems, Allegro PCB Designer, Cadence Allegro, Constraint Manager, SKILL, ODB++, IPC-2581, Gerber
3w
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Layout Design Engineer (SRAM)
Santa Clara, California, United States
$45k-$121k/yr OnsiteFull Time
10+ YOEBSEE or equivalent, 10+ years custom IC layout experience with 5+ years in SRAM/memory IP, advanced-node (FinFET/GAA) experience, Cadence Virtuoso and Calibre/ICV proficiency, DRC/LVS debugging, mentoring ability.
Cadence Virtuoso, Calibre, ICV
2w
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Electrical PCB Layout Engineer
South San Francisco, California, United States
OnsiteFull Time
Experienced PCB layout engineer skilled in Altium from schematic handoff through fabrication and assembly release, with knowledge of high-/low-speed, power, EMI/thermal, DFM/DFA, and cross-functional collaboration.
Altium Designer, Gerbers, ODB++
2d
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Package Design & Layout Engineer
Palo Alto, California, United States
OnsiteFull Time
6+ YOE6+ years IC package physical design experience, BS/MS in electrical engineering, expertise in package layout tools, multi-die packaging, substrate stack-ups, DFM/DF A closure, and English fluency.
Cadence Allegro Package Designer, APD+, Siemens Xpedition Package Designer, Synopsys IC Package, SKILL, Python, Cadence Sigrity, PowerSI, Ansys, Virtuoso, KLayout, AutoCAD, Cadence Integrity 3D-IC
1mo
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Sr PCB Layout Engineer, Amazon Leo
Austin or Sunnyvale or Redmond or New York or San Diego
$137k-$214k/yr OnsiteFull Time
7+ YOEBachelor's degree or equivalent, 7+ years PCB layout experience, 5+ years high-speed circuit experience, experience managing multiple projects, U.S. work-authorization required; Mentor Xpedition experience preferred.
Mentor Xpedition
1mo
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Staff PCB Layout Design Engineer
Mountain View or Sunnyvale
$218k-$245k/yr HybridFull Time
10+ YOEBachelor's in engineering required; 10 years experience in PCB layout and related roles; 8 years with design tools including Mentor Graphics; experience with HDI, high-power boards, high-speed buses, DFM/DFT, and leading design/supplier teams.
Mentor Graphics, ECAD
2mo
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Analog/RF IC Layout Design Engineer
Colorado Springs or Santa Clara
$120k-$200k/yr OnsiteFull Time
7+ YOEBS/MS in Electrical Engineering; 7+ years analog IC layout; 5+ years Cadence Virtuoso Layout XL; DRC/LVS/meter densities; BiCMOS 130 nm+; device matching knowledge; multi-design capability; SVN/Cliosoft/SOS experience; strong teamwork.
Cadence Virtuoso, DRC, LVS, Mentor Calibre, OCEAN, Scripting
1mo
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IC Layout Automation Software Engineer
Fremont, California, United States
$190k-$220k/yr OnsiteFull Time
BS (or higher) in a technical field, strong Python proficiency, experience with IC layout formats (GDSII) and EDA tools (KLayout, gdspy, Cadence), familiarity with semiconductor fabrication and lithography, and experience owning production software.
Python, GDSII, KLayout, gdspy, Cadence, EDA
2mo
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Analog/RF IC Layout Design Engineer.
Colorado Springs or Santa Clara
$118k-$196k/yr OnsiteFull Time
7+ YOEBS/MS in Electrical Engineering or equivalent,7+ years custom analog IC layout experience,5+ years Cadence Virtuoso Layout XL,sub-micron BiCMOS knowledge,device matching,version control experience,US export-control restrictions apply.
Cadence Virtuoso Layout XL, SVN, Cliosoft/SOS, Mentor Calibre, Linux, SKILL, OCEAN
1w
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Layout (FIRE) Extraction Engineer
Milpitas, California, United States
$120k-$160k/yr OnsiteFull Time
Bachelor's in electrical engineering or related, experience with OPC/RET and mask/CMOS processes, scripting (Python/Perl/Tcl/Shell), Linux, and collaboration with design/lithography/fab teams.
Mentor Graphics Calibre OPC/ILT, Synopsys Sentaurus/Litho, ASML Brion Tachyon, Cadence, Synopsys, KLayout, Linux, Python, Perl, Tcl, Shell
3d
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Senior Custom Memory Layout Design Engineer
Raleigh or Hillsboro or Austin or Mountain View or Redmond
$120k-$235k/yr HybridFull Time
1+ YOEDegree in EE/CE/CS (or equivalent) with 1+ to 5+ years experience depending on degree; experience in custom SRAM/RF/cache layout, physical verification, signoff, scripting (Python, SKILL, TCL, Perl) and advanced-node processes; must pass Microsoft cloud background and export-control eligibility checks.
Cadence Virtuoso, Siemens/Mentor Calibre, Ansys Totem, Cadence Voltus, Python, SKILL, TCL, Perl
1mo
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Digital Layout Design Engineer
Santa Clara, California, United States
OnsiteFull Time
Design custom digital macros and libraries for ASICs at advanced technology nodes; collaborate with integration, CAD, circuit, and technology engineering teams.