149 layout jobs at 59 companies in Marina, CA

1mo
Save
Mark Applied
Hide
Layout Designer
San Jose, California, United States
$46-$106/hr OnsiteFull Time
Micron Technology
Micron TechnologyNASDAQ: MU: Designs and manufactures semiconductor memory and data storage solutions.
5+ YOEAS in Electronics/Electrical Engineering plus 5+ years semiconductor layout experience; deep knowledge of EDA tools (Cadence Virtuoso, Synopsys, Calibre); strong debugging, physical verification, layout and floor/planning skills; strong communication.
EDA tools, Cadence Virtuoso, Synopsys, Calibre, Agentic AI
1mo
Save
Mark Applied
Hide
Senior Layout Designer
San Jose, California, United States
$63-$120/hr OnsiteFull Time
Micron Technology
Micron TechnologyNASDAQ: MU: Manufacturer of semiconductor memory and data storage products.
10+ YOEAssociate degree in electronics/electrical engineering plus 10 years layout experience; deep EDA tool knowledge; strong debugging, verification, communication, and layout methodology skills.
Cadence Virtuoso, Synopsys, Calibre
1mo
Save
Mark Applied
Hide
Senior PCB Layout Engineer
Sunnyvale, California, United States
$106k-$214k/yr OnsiteFull Time
Hewlett Packard Enterprise
Hewlett Packard EnterpriseNYSE: HPE: Provides global edge-to-cloud technology solutions and IT infrastructure services.
8+ YOE8+ years PCB layout experience, expert in Cadence Allegro, high-speed design, SI/PI and impedance control, HDI and manufacturing knowledge, ability to lead layout planning and mentor junior designers.
Cadence Allegro PCB Designer, Cadence Allegro, Constraint Manager, SKILL, ODB++, IPC-2581, Gerber
1d
Save
Mark Applied
Hide
Senior Package Layout Engineer - Hardware
Santa Clara or Nevada or Washington or Arizona or Oregon or California
$136k-$259k/yr HybridFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs graphics processing units and artificial intelligence hardware.
5+ YOEBachelor's degree in electrical engineering or equivalent experience, 5+ years of PCB layout experience, and expertise with Cadence APD or SiP, high-speed design, substrate layout, and PCB layout tools.
Cadence APD, SiP, Constraint Manager, Virtuoso, Calibre, Valor, CAD
2mo
Save
Mark Applied
Hide
Staff Analog Layout Engineer
San Jose or Hsinchu
OnsiteFull Time
Neurophos
Neurophos: Develops high-performance photonic processors for AI inference acceleration.
3+ YOESenior/Staff level IC layout engineer with 3-8+ years in deep-submicron analog/RF layouts; strong EDA/tool experience and EM/IR knowledge.
Cadence Virtuoso, Synopsys Custom Compiler, Mentor Calibre, Siemens ICV
1d
Save
Mark Applied
Hide
Senior Package Layout Engineer - Hardware
Santa Clara or Nevada or Oregon or Arizona or Washington or California
$136k-$259k/yr HybridFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs GPU-accelerated computing and artificial intelligence hardware.
5+ YOEBachelor's degree in electrical engineering or equivalent experience; 5+ years in PCB layout; substrate layout, Cadence APD or SiP, high-speed signal integrity, and related CAD tools required or preferred.
Cadence APD, SiP, Constraint Manager, Virtuoso, Calibre, Valor
1mo
Save
Mark Applied
Hide
Senior PCB Layout Engineer
Sunnyvale, California, United States
$106k-$214k/yr OnsiteFull Time
Hewlett Packard Enterprise
Hewlett Packard EnterpriseNYSE: HPE: Provides edge-to-cloud IT infrastructure and platform services.
8+ YOE8+ years PCB layout experience; expert in Cadence Allegro and Constraint Manager; strong high-speed design, SI/PI, HDI, impedance control, and PCB manufacturing knowledge.
Cadence Design Systems, Cadence Allegro PCB Designer, Cadence Allegro, Constraint Manager, SKILL, ODB++, IPC-2581, Gerber
1mo
Save
Mark Applied
Hide
Senior PCB Layout Engineer
Sunnyvale, California, United States
$106k-$214k/yr OnsiteFull Time
Hewlett Packard Enterprise
Hewlett Packard EnterpriseNYSE: HPE: Providing global edge-to-cloud infrastructure and IT solutions for businesses.
8+ YOE8+ years PCB layout experience with expert Cadence Allegro proficiency, high-speed design, impedance/stackup planning, HDI, EMI/EMC, PCB fabrication knowledge, and mentoring experience.
Cadence Design Systems, Allegro PCB Designer, Cadence Allegro, Constraint Manager, SKILL, ODB++, IPC-2581, Gerber
3w
Save
Mark Applied
Hide
Layout Design Engineer (SRAM)
Santa Clara, California, United States
$45k-$121k/yr OnsiteFull Time
Wipro
WiproNYSE: WIT: Global technology services and consulting for digital transformation.
10+ YOEBSEE or equivalent, 10+ years custom IC layout experience with 5+ years in SRAM/memory IP, advanced-node (FinFET/GAA) experience, Cadence Virtuoso and Calibre/ICV proficiency, DRC/LVS debugging, mentoring ability.
Cadence Virtuoso, Calibre, ICV
1w
Save
Mark Applied
Hide
Staff Engineer, PCB Layout
San Jose, California, United States
$150k-$240k/yr OnsiteFull Time
Celestica
CelesticaNYSE: CLS: Provides design, manufacturing, and supply chain solutions for electronics.
7+ YOE7+ years PCB layout experience with Cadence Allegro (16.x/17.x), high-density and high-speed designs, knowledge of PCB/PCBA manufacturing, IPC standards, signal integrity, EMC/EMI; bachelor's degree or equivalent.
Cadence Allegro, Valor Trilogy 5000
2mo
Save
Mark Applied
Hide
Staff Custom Analog Layout Engineer
San Jose or United States
$139k-$259k/yr HybridFull Time
Nokia
NokiaNYSE: NOK: Sells telecommunications infrastructure and software for global network operators.
10+ YOEBS degree or equivalent; 10+ years in analog/mixed-signal layout design; proficient with layout tools and DRC/LVS/ERC flows.
Virtuoso, Laker, Calibre, PVS, IC Validator, DRC/LVS/ERC tools, RC extraction, EM/IR analysis
2w
Save
Mark Applied
Hide
IC Package Layout Team Leader
San Jose, California, United States
$211k-$305k/yr HybridFull Time
Cisco
CiscoNASDAQ: CSCO: Develops and sells networking hardware and cybersecurity software.
5+ YOEDegree in electrical engineering with relevant experience, 5+ years package/layout experience, high-speed routing and PDN knowledge, EDA tool proficiency, and leadership/mentorship experience.
Cadence APD+, Python, Perl, TCL
1mo
Save
Mark Applied
Hide
Sr PCB Layout Engineer, Amazon Leo
Austin or Sunnyvale or Redmond or New York or San Diego
$137k-$214k/yr OnsiteFull Time
Amazon
AmazonNASDAQ: AMZN: Global online retail and cloud computing technology provider.
7+ YOEBachelor's degree or equivalent, 7+ years PCB layout experience, 5+ years high-speed circuit experience, experience managing multiple projects, U.S. work-authorization required; Mentor Xpedition experience preferred.
Mentor Xpedition
1mo
Save
Mark Applied
Hide
Staff PCB Layout Design Engineer
Mountain View or Sunnyvale
$218k-$245k/yr HybridFull Time
General Motors
General MotorsNYSE: GM: Manufactures and sells automobiles and automotive parts globally.
10+ YOEBachelor's in engineering required; 10 years experience in PCB layout and related roles; 8 years with design tools including Mentor Graphics; experience with HDI, high-power boards, high-speed buses, DFM/DFT, and leading design/supplier teams.
Mentor Graphics, ECAD
2mo
Save
Mark Applied
Hide
Analog/RF IC Layout Design Engineer.
Colorado Springs or Santa Clara
$118k-$196k/yr OnsiteFull Time
Keysight Technologies
Keysight TechnologiesNew York Stock Exchange: KEYS: Manufactures hardware and software for electronic test and measurement.
7+ YOEBS/MS in Electrical Engineering or equivalent,7+ years custom analog IC layout experience,5+ years Cadence Virtuoso Layout XL,sub-micron BiCMOS knowledge,device matching,version control experience,US export-control restrictions apply.
Cadence Virtuoso Layout XL, SVN, Cliosoft/SOS, Mentor Calibre, Linux, SKILL, OCEAN
1w
Save
Mark Applied
Hide
Digital Layout Design Engineer
Santa Clara, California, United States
OnsiteFull Time
Apple
AppleNASDAQ: AAPL: Designs and sells consumer electronics, software, and online services.
Design custom digital macros and libraries for state-of-the-art ASICs at advanced technology nodes; collaborate with integration, CAD, circuit, and technology engineering teams.
CAD, ASIC
1mo
Save
Mark Applied
Hide
Principal/Senior High-Speed Analog Layout Engineer
Irvine or San Jose or Ottawa
OnsiteFull Time
Celero Communications
Celero Communications: Developing high-performance coherent DSP technology for AI connectivity.
10+ YOE10+ years analog/mixed-signal layout experience in advanced CMOS/FinFET (TSMC preferred), expertise with Cadence Virtuoso, Calibre, Pegasus, LVS/DRC/PERC/ERC flows, and leadership/mentoring experience; scripting with SKILL/TCL/Python a plus.
Cadence Virtuoso, Calibre, Pegasus, SKILL, TCL, Python
3w
Save
Mark Applied
Hide
Head of Cinematography, Layout- Ink
Los Angeles or Vancouver or Los Gatos
$75/hr OnsiteFull Time
Netflix
NetflixNASDAQ: NFLX: Provider of global streaming entertainment and video content.
7+ YOE4+ Mgmt7+ years in film/TV/games, 4+ years leading teams, credits in layout/previs, knowledge of previs/camera/CG shot production, Maya/Houdini/Nuke, Python/MEL familiarity, GenAI tool interest, budget and timeline experience.
Autodesk Maya, Houdini, Nuke, Python, MEL
2mo
Save
Mark Applied
Hide
Senior Staff Hardware Design Engineer - PCB layout and fabrication and mixed-signal design and ODSP and AEC and PCIe
Santa Clara, California, United States
$128k-$191k/yr OnsiteFull Time
Marvell
MarvellNASDAQ: MRVL: Designs and develops high-performance semiconductor and infrastructure solutions.
3+ YOEBS/MS/PhD in Electrical Engineering; 8+ yrs (Bachelors), 5+ (Masters), or 3+ (PhD); PCB layout tools; PCB fabrication/assembly; high-speed mixed-signal design; signal/power integrity; active/passive components; IEEE 802.3 and optical module/AEC MSAs; strong communication; self-motivated and team-oriented.
PCB layout tools, PCB fabrication, signal integrity, power integrity
1w
Save
Mark Applied
Hide
Sr. Staff Engineer, Analog/Mixed-Signal Design
San Jose, California, United States
$180k-$223k/yr OnsiteFull Time
Ayar Labs
Ayar Labs: Develops optical interconnect technology for high-speed data movement.
6+ YOEM.S. in Electrical Engineering,6+ years analog/mixed-signal design,experience with high-speed analog blocks and FinFET CMOS,proficient with Cadence/ADE/Layout/Spectre;Python and SKILL preferred.
Cadence, ADE, Layout, Spectre, Python, SKILL