Pacific Grove • 50 milesRemote · Hybrid · Onsite · Field · All Environments
Pacific Grove • 50 milesRemote · Hybrid · Onsite · Field · All Environments
Pacific Grove • 50 milesRemote · Hybrid · Onsite · Field · All Environments
Pacific Grove • 50 milesRemote · Hybrid · Onsite · Field · All Environments
79 layout jobs at 34 companies in Pacific Grove, CA
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Layout Designer
San Jose, California, United States
$46-$106/hr OnsiteFull Time
5+ YOEAS in Electronics/Electrical Engineering plus 5+ years semiconductor layout experience; deep knowledge of EDA tools (Cadence Virtuoso, Synopsys, Calibre); strong debugging, physical verification, layout and floor/planning skills; strong communication.
EDA tools, Cadence Virtuoso, Synopsys, Calibre, Agentic AI
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Senior Layout Designer
San Jose, California, United States
$63-$120/hr OnsiteFull Time
10+ YOEAssociate degree in electronics/electrical engineering plus 10 years layout experience; deep EDA tool knowledge; strong debugging, verification, communication, and layout methodology skills.
Cadence Virtuoso, Synopsys, Calibre
2mo
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Staff Analog Layout Engineer
San Jose or Hsinchu
OnsiteFull Time
3+ YOESenior/Staff level IC layout engineer with 3-8+ years in deep-submicron analog/RF layouts; strong EDA/tool experience and EM/IR knowledge.
Cadence Virtuoso, Synopsys Custom Compiler, Mentor Calibre, Siemens ICV
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Staff Engineer, PCB Layout
San Jose, California, United States
$150k-$240k/yr OnsiteFull Time
7+ YOE7+ years PCB layout experience with Cadence Allegro (16.x/17.x), high-density and high-speed designs, knowledge of PCB/PCBA manufacturing, IPC standards, signal integrity, EMC/EMI; bachelor's degree or equivalent.
Cadence Allegro, Valor Trilogy 5000
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Staff Custom Analog Layout Engineer
San Jose or United States
$139k-$259k/yr HybridFull Time
10+ YOEBS degree or equivalent; 10+ years in analog/mixed-signal layout design; proficient with layout tools and DRC/LVS/ERC flows.
Virtuoso, Laker, Calibre, PVS, IC Validator, DRC/LVS/ERC tools, RC extraction, EM/IR analysis
2w
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IC Package Layout Team Leader
San Jose, California, United States
$211k-$305k/yr HybridFull Time
5+ YOEDegree in electrical engineering with relevant experience, 5+ years package/layout experience, high-speed routing and PDN knowledge, EDA tool proficiency, and leadership/mentorship experience.
Cadence APD+, Python, Perl, TCL
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Sr. Package Layout Engineer, Annapurna Labs - AI Silicon Packaging
Tempe or Austin or Cupertino
$159k-$248k/yr OnsiteFull Time
10+ YOEBachelor's in EE or related, 10+ years IC package layout and physical design experience, expertise with advanced packaging (2.5D/3D, WLP, RDL, TSV), package DRC/DFM, and collaboration with SI/PI and manufacturing teams.
Cadence APD/SiP, Synopsys IC Packaging, Mentor Xpedition, Python, TCL, Skill, Ravel
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Principal/Senior High-Speed Analog Layout Engineer
Irvine or San Jose or Ottawa
OnsiteFull Time
10+ YOE10+ years analog/mixed-signal layout experience in advanced CMOS/FinFET (TSMC preferred), expertise with Cadence Virtuoso, Calibre, Pegasus, LVS/DRC/PERC/ERC flows, and leadership/mentoring experience; scripting with SKILL/TCL/Python a plus.
Cadence Virtuoso, Calibre, Pegasus, SKILL, TCL, Python
3w
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Head of Cinematography, Layout- Ink
Los Angeles or Vancouver or Los Gatos
$75/hr OnsiteFull Time
7+ YOE4+ Mgmt7+ years in film/TV/games, 4+ years leading teams, credits in layout/previs, knowledge of previs/camera/CG shot production, Maya/Houdini/Nuke, Python/MEL familiarity, GenAI tool interest, budget and timeline experience.
Autodesk Maya, Houdini, Nuke, Python, MEL
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Sr. Staff Engineer, Analog/Mixed-Signal Design
San Jose, California, United States
$180k-$223k/yr OnsiteFull Time
6+ YOEM.S. in Electrical Engineering,6+ years analog/mixed-signal design,experience with high-speed analog blocks and FinFET CMOS,proficient with Cadence/ADE/Layout/Spectre;Python and SKILL preferred.
Cadence, ADE, Layout, Spectre, Python, SKILL
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RFIC Design Intern
San Jose, California, United States
OnsiteMultiple Commitments Available
2+ YOECurrently pursuing M.S. or Ph.D. in Electrical Engineering, 2+ years RFIC design experience, familiarity with CMOS/SOI/SiGe, RF layout and post-layout simulation, Cadence Virtuoso, Spectre RF, ADS, Python or MATLAB.
Cadence Virtuoso, Spectre RF, ADS, Python, MATLAB
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Sales FAE
San Jose, California, United States
HybridFull Time
BS in electrical engineering; MS preferred; experience with electronic components; board design/layout; good English; travel willingness.
MS Office, Oscilloscope, DVM, Signal Generator
3d
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Packaging Design Engineer
San Jose or San Diego
HybridFull Time
Experienced package engineer with CAD/simulation tool proficiency, package/PCB layout and power integrity expertise, scripting ability, and engineering degree.
Cadence, SKILL, Ansys, AutoCAD
3mo
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Hardware Systems Engineering Lead – Biophotonics
Cupertino or United States
OnsiteFull Time
10+ YOEBS in EE or related field; 10+ years exp; strong analog/digital circuit design; PCB layout; multi-discipline collaboration.
Eagle, Altium, Cadence, Hspice, LTspice, Spectre, PCB Layout, ANYSYS, Verilog-AMS, Simulink, COMSOL
2mo
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Art Director
Hong Kong or San Jose
OnsiteFull Time
5+ YOE5+ years in design/art direction; strong typography, layout, color; leadership with hands-on execution; game or creative design experience a plus.
1mo
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Foreman
San Jose, California, United States
$160k-$165k/yr OnsiteFull Time
5+ YOEMinimum five years commercial construction experience with leadership; advanced carpentry, layout, plan-reading, safety, QA/QC, scheduling, and crew supervision skills.
1w
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HVAC Installer Journeyman
Campbell, California, United States
$28-$34/hr OnsiteFull Time
5+ YOE5+ years residential HVAC construction experience, ability to lift heavy objects, lead crews, read fabrication/layouts, follow HVAC code, and communicate with supervisors.
2w
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System Architecture Engineer
San Jose, California, United States
$127k-$175k/yr OnsiteFull Time
2+ YOEBachelor's in EE or related, 2+ years in power electronics, expertise in high-voltage power converters, PCB layout, test equipment, soldering, and EDA/simulation tools.
Cadence Allegro, Altium Designer, Simetrix/Simplis, Mathcad, PLECS, PSIM, Gerber, BOM, oscilloscopes, thermal cameras, programmable DC power supplies, electronic loads
2w
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Principle Design Engineer (ADC expertise)
San Jose, California, United States
OnsiteFull Time
Experience in high-resolution ADC circuit design, proficiency with Cadence/Mentor EDA tools, strong layout knowledge, digital integration experience, and effective written and verbal communication.
Cadence, Mentor, EDA
1w
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Staff RFIC Design Engineer
San Jose, California, United States
$120k-$160k/yr OnsiteFull Time
10+ YOEHands-on analog/mixed-signal IC design experience in CMOS (40nm and below), EDA tool proficiency, layout and reliability knowledge, and demonstrated mass-production design releases.
Cadence, Mentor, Siemens, Ansys