3mo
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RTL Design Engineer
Waltham, Massachusetts, United States
OnsiteFull Time
Bachelor's in Electrical Engineering; RTL design experience; Verilog/SystemVerilog; front-end tools; mixed-signal and analog concepts; scripting (Perl, JSON, Python); GenAI tooling for RTL design.
Verilog, SystemVerilog, Verilog simulators, UPF, Python, Perl, JSON
1mo
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Interconnect Micro-architect/RTL Design Engineer
Austin or Boxborough
$156k-$268k/yr HybridFull Time
Experienced RTL design engineer with strong Verilog/System Verilog skills, knowledge of C/C++ and scripting (Perl or Python), digital/high-speed design understanding, and experience with multi-processor coherency, DFT-friendly RTL and post-silicon debug.
Verilog, System Verilog, C, C++, Perl, Python, x86, ARM
3mo
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Senior Staff RTL Design Engineer- 16908
Boxborough, Massachusetts, United States
$138k-$208k/yr OnsiteFull Time
10+ YOE10+ years ASIC digital design experience with production RTL ownership, Verilog and Perl proficiency, knowledge of synthesis, timing analysis, and power optimization; Bachelor's degree in EE/CE or related field required.
Verilog, Perl
3mo
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RTL Design Engineer (North Reading, MA, US)
North Reading, Massachusetts, United States
$123k-$197k/yr OnsiteFull Time
5+ YOEBSEE or MSEE with 5+ years; extensive RTL Verilog; CDC/STA; memory/serial interfaces; scripting (Python, Tcl, Make).
Verilog, Python, Tcl, Make
1w
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Principal PCIe Subsystem RTL lead
San Jose or Santa Clara or Austin or Seattle or Boston
HybridFull Time
10+ YOE10+ years digital IC design experience with 4+ years PCIe subsystem design/integration, strong SystemVerilog RTL skills, experience integrating PCIe controller/SerDes PHY, multi-clock-domain design, and ability to lead architectural work.
SystemVerilog, UVM, PCIe, CXL, SerDes
2mo
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Distinguished Engineer, ASIC (CONTRACT)
Burlington or New York or San Francisco
HybridContract, Temporary
8+ YOE8–12+ years in digital IC/ASIC/SoC design; strong RTL SystemVerilog; tapeout experience; cross-functional collaboration.
SystemVerilog, Verilog, RTL, ASIC, SoC, clock_domain, PPA tools
2mo
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Software Engineer II (Full Stack, Platform)
Boston, Massachusetts, United States
$125k-$175k/yr OnsiteFull Time
3+ YOE2–4 years experience; JS/TypeScript, React, Node.js; REST APIs; i18n, RTL; UI components; CI/CD; collaboration.
JavaScript, TypeScript, React, Node.js, REST APIs, PostgreSQL, MySQL, CircleCI, GitHub Actions, Figma, CSS, WCAG, Storybook, i18n, RTL, BiDi
2mo
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Principal Firmware/FPGA Engineer (Onsite)
Cambridge, Massachusetts, United States
$108k-$205k/yr OnsiteFull Time
8+ YOE8+ years in STEM or an advanced degree with 5+ years; FPGA RTL/Verilog/VHDL; DSP fundamentals; high-speed interfaces; scripting; ability to obtain security clearance
Verilog, VHDL, RTL, FPGA, C++, Python, bash, Tcl, Ethernet, sFPDP, HBM2, DDR, Linux, Petalinux
3w
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Physical Design Engineer
Beaver Brook or Phoenix
$122k-$200k/yr OnsiteFull Time
2+ YOEExperience implementing physical design flows for custom IP/SoC, proficiency with EDA tools, RTL/GDS knowledge, scripting (TCL), and 2+ years of relevant experience with a relevant degree.
industry-standard EDA tools, TCL, RTL, GDS
2mo
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Senior Engineer, Digital Design Engineering
Wilmington, Massachusetts, United States
$124k-$175k/yr HybridFull Time
2+ YOEMaster’s degree in Electrical/Electronic/Computer Engineering or related field; 2+ years in digital/mixed-signal design and verification; proficiency with RTL, Verilog/SystemVerilog; experience with Cadence or Synopsys tools.
Verilog, SystemVerilog, RTL, Cadence, Synopsys
2mo
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FPGA Engineer (MA, Boston)
Boston, Massachusetts, United States
OnsiteFull Time
EndoSec: Security software and cryptographic hardware for government and defense.
Experience with RTL, HDL, C/C++, Python; VHDL/Verilog; hardware security; IP core development; FPGA toolchains; Xilinx/Intel devices; simulation and verification; system integration; embedded software testing; cryptography; cocotb/pyuvm.
RTL, VHDL, Verilog, Python, C, C++, Tcl, Vivado, GHDL, Questa, Quartus Prime, Zynq, Versal, Stratix, Agilex, AXI, ACE, Avalon, IP core, Xilinx, FPGA verification tools, cocotb, pyuvm
1mo
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FPGA Engineer
Boston, Massachusetts, United States
OnsiteFull Time
RTL proficiency (Verilog or VHDL), real industry FPGA deployment experience, familiarity with major FPGA platforms (Xilinx/AMD, Lattice, Intel/Altera), embedded C/C++ experience, and experience with prototype bring-up and ASIC verification workflows.
Verilog, VHDL, C, C++, RTL, FPGA, Xilinx, AMD, Lattice, Intel/Altera, ASIC, ADC, DAC
1mo
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Modem HW Design Verification Engineer – AI Driven Next Gen Modem Hardware Development
San Diego or Santa Clara or Boxborough
$128k-$192k/yr OnsiteFull Time
1+ YOEDegree in computer/electrical engineering or related field (BS/MS/PhD) with 1+ years (MS) or 2+ years (BS) engineering experience. Experience in verification planning, SystemVerilog/UVM, RTL languages, C/C++, Python/Perl, Unix/Linux scripting, and GenAI/ML-assisted verification preferred.
SystemVerilog, UVM, OVM, Verilog, VHDL, C, C++, SystemC, Python, Perl, Unix/Linux shell scripting, Makefiles, XML, RTL
2w
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Interconnect Design Engineer
Santa Clara or Cambridge or Austin or Boston
$206k-$251k/yr OnsiteFull Time
Expertise in interconnect, cache/coherency and RTL generator design; strong software engineering and hardware RTL skills; BS/MS in EE/CE/CS or equivalent experience.
Chisel, Scala, FIRRTL, Verilog, System Verilog, VHDL, Bluespec, Git, Github, Jira, Confluence, TileLink, RISC-V, AXI, AHB, APB, CHI
2mo
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Senior Digital Engineer
Sydney or Sydney or Irvine or Boston or Bangalore or Cambridge or Hangzhou or Taipei or Tokyo or Sydney
OnsiteFull Time
5+ YOE5+ years as Senior Digital Engineer; strong Verilog/SystemVerilog; RTL design; low-power techniques; collaborate with firmware/PHY teams.
Verilog/SystemVerilog, C, Python, Tcl, Shell, Makefiles, UPF/CPF, Scripting and automation
1w
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Clinic Coordinator - Mon-Fri 9:30am-6pm
Newton, Massachusetts, United States
$46k-$54k/yr OnsiteFull Time
High school diploma required (bachelor's preferred). Customer-service experience preferred. Proficiency with Epic, RTLS, Outlook and complex computer systems. Strong communication, organization, and scheduling skills.
Epic, Real Time Locating System (RTLS), Microsoft Outlook, Partners Patient Gateway, MASS HiWay, Health Stream, iPad
2w
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Principal FPGA Digital Design Engineer - Sign-on Bonus
Nashua, New Hampshire, United States
OnsiteFull Time
6+ YOESecret-clearable engineer with 6+ years FPGA/ASIC experience, VHDL/Verilog RTL coding, timing closure, lab debug, familiarity with high-speed interfaces and revision control.
VHDL, Verilog, Xilinx Vivado, Intel/Altera Quartus, ChipScope, SignalTap, ILA, Modelsim, Questa, GIT, CVS, Clearcase, Subversion, Perl, Tcl, Python, shell, Matlab, Simulink, UVM, SystemVerilog, C, C++
1d
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Electrical Engineer
Marlborough, Massachusetts, United States
$75k-$99k/yr OnsiteFull Time
1+ YOEBS/MS in Electrical or Computer Engineering,1-4 years EE experience,schematic design and FPGA RTL with Verilog,OrCAD proficiency,technical writing and strong communication skills.
OrCAD, Verilog, ModelSim, Quartus, Git, SVN, oscilloscope, logic analyzer, frequency generator
3w
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Senior ASIC Hardware Design Engineer
Westford, Massachusetts, United States
$136k-$265k/yr OnsiteFull Time
5+ YOEBachelor's or Master's in EE/CE/CS (or equivalent) with 5+ years industry experience; strong Verilog/SystemVerilog and RTL/microarchitecture experience; scripting in Perl or Python; understanding of physical implementation and VLSI.
Verilog, SystemVerilog, Perl, Python
3w
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Senior ASIC Hardware Design Engineer
Westford, Massachusetts, United States
$136k-$265k/yr OnsiteFull Time
5+ YOEBachelors in EE/CE/CS (or equivalent) and 5+ years experience; strong Verilog/SystemVerilog skills, RTL/micro-architecture experience, Python/Perl scripting, understanding of physical implementation and VLSI.
Verilog, SystemVerilog, Perl, Python
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