18 rtl engineer jobs at 13 companies in Clark, NJ
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RTL Design Engineer
New York City or Palo Alto or London
$205k-$285k/yr HybridFull Time
Production SystemVerilog RTL experience, verification with UVM/cocotb/formal, taped-out silicon, ASIC/SoC design background, simulation and timing collaboration experience.
SystemVerilog, UVM, cocotb, formal, Chipyard, OpenTitan, CVA6, RISC-V
4w
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Hardware Engineer, RTL/PD
New York City or London or Zurich or Palo Alto or Copenhagen or Seoul
$200k-$285k/yr OnsiteFull Time
Production SystemVerilog RTL experience, synthesis and place-and-route through tapeout, experience with backend flows and timing closure, familiarity with formal methods and post-silicon bring-up; multiple tapeouts preferred.
SystemVerilog, RISC-V, GDSII, CTS, DFT, LVS, DRC
2mo
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Senior FPGA Engineer
Chicago or New York City or London
$225k-$325k/yr OnsiteFull Time
3+ YOEBachelor's in Computer or Electrical Engineering, 3+ years FPGA/hardware engineering experience, RTL/Verilog expertise, FPGA design flow experience, knowledge of TCP/IP, strong autonomous and problem-solving skills.
Verilog, System Verilog, RTL, XILINX, ALTERA, TCP/IP, synthesis, place & route, static timing analysis
2w
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Hardware Design Engineer
Tempe or San Jose or San Francisco or New York City
$133k-$210k/yr OnsiteFull Time
4+ YOEBachelor's degree or equivalent in electrical or computer engineering, 4+ years in high-speed digital board design and FPGA/RTL development, US citizenship, Secret clearance eligibility, and up to 10% travel.
SystemVerilog, Verilog, VHDL, AMD Vivado, Intel Quartus, Synopsys Synplify, Mentor Xpedition, Cadence, Altium, HyperLynx, Python, TCL, Perl, ModelSim, Questa, Git, Claude Code, Copilot, DDR4, SERDES, UART, I2C, SPI, LVDS, FPGA, RTL, SoC, ADC, DAC, CI/CD, AI
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FPGA Engineer - Control Systems
Princeton, New Jersey, United States
$150k-$235k/yr OnsiteFull Time
Experienced in FPGA/ASIC digital logic design and verification, RTL and low-latency firmware for multi-domain clock systems; familiarity with Xilinx/AMD RFSoC platforms preferred.
RTL, FPGAs, ASICs, Xilinx, AMD, RFSoC
2w
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ML ASIC Design Engineer
Mountain View or New York City
$175k-$215k/yr HybridFull Time
5+ YOEBS in Computer Engineering or equivalent experience; 5+ years with SystemVerilog, ASIC RTL design, and microarchitecture; 3+ years designing high-performance CPU, GPU, or NPU cores; Python or C++.
SystemVerilog, Python, C++, Chisel, Scala
3mo
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Senior Engineer, Digital Design Engineering
Somerset, New Jersey, United States
$127k-$175k/yr HybridFull Time
2+ YOEMaster’s degree in Electrical/Electronic/Computer Engineering or related field; 2+ years in digital design/mixed-signal verification; experience with RTL, Verilog/SystemVerilog, and ASIC/FPGA design flows.
Verilog, SystemVerilog, Cadence, Synthesis, CDC, Verifications tools
3w
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ASIC Engineer
New York City, New York, United States
$250k-$300k/yr OnsiteFull Time
4+ YOE4+ years RTL design and verification experience; ASIC design using Synopsys or Cadence flows; experience in front-end, back-end or verification; FPGA/ASIC familiarity; programming experience (Python, C++, Java, Haskell); willingness to learn OCaml.
Hardcaml, OCaml, Synopsys, Cadence, Python, C++, Java, Haskell
1mo
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Two Sigma Securities, Hardware Engineer
New York City, New York, United States
$165k-$300k/yr HybridFull Time
1+ YOEMinimum 1 year RTL design and verification experience, proficiency in SystemVerilog and Python, FPGA/ASIC knowledge, timing analysis, network protocol familiarity; C++ is a plus.
SystemVerilog, Python, FPGA, ASIC, C++
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FPGA Engineer – Intern (US)
New York or Miami
$5k-$6k/wk OnsiteInternship
Pursuing a Bachelor's, Master's or PhD in EE/CE or related field; experience with SystemVerilog or VHDL; knowledge of hardware architecture, RTL, simulation, validation, FPGA synthesis; strong communication and problem-solving skills.
SystemVerilog, VHDL, Python, C, Tcl, Bash
1mo
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FPGA Design Engineer
New York City, New York, United States
$200k-$280k/yr OnsiteFull Time
Proven FPGA experience bringing RTL to timing-closed hardware; expert SystemVerilog/VHDL and Xilinx Vivado; PCIe and common bus protocols; strong Python/C++ for automation; board bring-up and lab debugging skills.
SystemVerilog, VHDL, Xilinx Vivado, ILA, Vivado Analyzer, Python, C++, PCIe, AXI, AHB, SPI, UART, JTAG, HAPS, VCU118, VPK180, Cocotb, UVM, OSVVM, hls4ml, FINN, GitLab CI, Docker, oscilloscope, logic analyzer
3w
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ASIC Physical Design Engineer
New York City, New York, United States
$250k-$300k/yr OnsiteFull Time
8+ YOE8+ years building and running physical design flows; ability to own PD flow end-to-end, read and write RTL, and use high-level programming to improve hardware tools.
Hardcaml, OCaml, Python, C++, Haskell
1mo
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Research Engineer, Chip Design RL (Reinforcement Learning)
San Francisco or New York City
$500k-$850k/yr HybridFull Time
Bachelor's or equivalent, expertise in ASIC/FPGA design and EDA tools, experience with RTL, verification (UVM, formal methods), physical design and tapeout experience; RL experience and tooling experience preferred.
EDA tools, UVM, formal methods, place-and-route
3mo
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FPGA Engineer
Hong Kong or London or New York or Singapore or Sydney
$125k-$350k/yr OnsiteFull Time
Bachelor’s/Master’s/PhD in EE, CS, or CE; strong System Verilog/VHDL; hardware/RTL design; low-latency trading knowledge; good communication.
SystemVerilog, VHDL, Python, C, Tcl, Bash
1w
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2027 PhD Research Engineering Intern/Co-op
Austin or Boxborough or Fort Collins or Longmont or Fishkill or Rochester or Secaucus
$92k-$137k/yr HybridInternship, Temporary
Current PhD student at a US university in computer science, computer engineering, electrical engineering, or related field; knowledge of listed programming, hardware, ML, or systems technologies encouraged.
C, C++, Verilog HDL, Python, P4, ML frameworks, Java, MATLAB, Go, FPGA, ASIC, RTL, GPUs, PyTorch, TensorFlow
1w
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ASIC Technical Leader - Product Quality & Productization (Hybrid)
San Jose or New York City
$214k-$310k/yr HybridFull Time
20+ YOE20+ years in silicon DFT, test, quality, and program management, including 5+ years in high-reliability hardware; ASIC lifecycle expertise, Synopsys tools, ATE testers, and an electrical or computer engineering degree.
JTAG, SCAN, BIST, RTL, Synopsys, Design Compiler, Tetramax, Spyglass, VCS, ATE, 93K, SPC, JMP, Python, SQL, ISO 9001
1d
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ASIC Technical Project Manager
New York City, New York, United States
$150k-$250k/yr OnsiteFull Time
Technical project or engineering program management experience in semiconductor or ASIC hardware, electrical engineering background or hands-on ASIC experience, ASIC lifecycle knowledge, vendor experience, and project-tool proficiency.
Microsoft Project, Jira, RTL, GDSII
1d
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ASIC Technical Project Manager
New York City, New York, United States
$150k-$250k/yr OnsiteFull Time
Technical project management experience in semiconductor or ASIC hardware, electrical engineering background or hands-on ASIC experience, ASIC lifecycle knowledge, cross-functional program delivery, and project tracking tool proficiency.
Microsoft Project, Jira, RTL, GDSII, DFT, ECOs
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