44 asic engineer jobs at 21 companies in Clark, NJ
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ASIC Engineer
New York City, New York, United States
$250k-$300k/yr OnsiteFull Time
4+ YOE4+ years RTL design and verification experience; ASIC design using Synopsys or Cadence flows; experience in front-end, back-end or verification; FPGA/ASIC familiarity; programming experience (Python, C++, Java, Haskell); willingness to learn OCaml.
Hardcaml, OCaml, Synopsys, Cadence, Python, C++, Java, Haskell
2w
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ML ASIC Design Engineer
Mountain View or New York City
$175k-$215k/yr HybridFull Time
5+ YOEBS in Computer Engineering or equivalent experience; 5+ years with SystemVerilog, ASIC RTL design, and microarchitecture; 3+ years designing high-performance CPU, GPU, or NPU cores; Python or C++.
SystemVerilog, Python, C++, Chisel, Scala
1mo
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Hardware Engineer (FPGA/ASIC)
New York, New York, United States
$300k/yr OnsiteInternship
Comfortable with a programming language; experience with hardware description languages (VHDL, Verilog, Chisel, Pymtl) and FPGA/ASIC projects; familiar with vendor tools (Vivado, Quartus, Genus, Innovus).
Hardcaml, OCaml, VHDL, Verilog, Chisel, Pymtl, Vivado, Quartus, Genus, Innovus
21h
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ASIC Technical Project Manager
New York City, New York, United States
$150k-$250k/yr OnsiteFull Time
Technical project or engineering program management experience in semiconductor or ASIC hardware, electrical engineering background or hands-on ASIC experience, ASIC lifecycle knowledge, vendor experience, and project-tool proficiency.
Microsoft Project, Jira, RTL, GDSII
1w
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ASIC Technical Leader - Product Quality & Productization (Hybrid)
San Jose or New York City
$214k-$310k/yr HybridFull Time
20+ YOE20+ years in silicon DFT, test, quality, and program management, including 5+ years in high-reliability hardware; ASIC lifecycle expertise, Synopsys tools, ATE testers, and an electrical or computer engineering degree.
JTAG, SCAN, BIST, RTL, Synopsys, Design Compiler, Tetramax, Spyglass, VCS, ATE, 93K, SPC, JMP, Python, SQL, ISO 9001
4w
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Senior Engineer, Physical Design Engineering (ASIC)
Somerset County or Wilmington
$117k-$161k/yr OnsiteFull Time
5+ YOEExpertise in ASIC/SoC physical design, floorplanning, P&R, timing closure, physical verification, scripting (TCL/Python), and cross-functional collaboration; 5+ years experience preferred.
Cadence, TCL, Python
3d
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2027 Masters ASIC Package Engineering Co-op/Intern
Austin or Boxborough or Fishkill or Fort Collins or Longmont or Secaucus
$80k-$120k/yr HybridInternship, Contract
Currently enrolled in a U.S. master's program in engineering or related field; knowledge of circuits, package/PCB design software, Perl, Python, SQL, semiconductor packaging, or data analytics preferred.
Perl, Python, SQL, Power BI
3w
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Hardware Engineer III
Gurgaon or New York City
HybridFull Time
3+ YOEBachelor's degree in electrical engineering or equivalent experience; 3–5 years in ASIC/FPGA development and verification; expertise in Verilog, SystemVerilog/VHDL, Xilinx tools, networking, Linux, Python, and C/C++.
Verilog, SystemVerilog, VHDL, Xilinx, cocotb, UVM, Linux, Shell scripting, Python, C, C++, FPGA, ASIC, Ethernet, PCIe
4d
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Systems Engineer, Digital Payload
Tempe or San Jose or California or New York City or New York
$181k-$285k/yr OnsiteFull Time
8+ YOEBachelor's degree or equivalent experience and 8+ years in systems engineering, digital payloads, FPGA/ASIC systems, aerospace, space, or mission-critical systems; requires hardware-description-language proficiency and technical leadership.
FPGA, ASIC, DSP, VHDL, Verilog, SystemVerilog, SERDES, DVB-S2, DVB-S2X, DVB-RCS, 3GPP, MBSE
2mo
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AI Research Engineer, Pre-Training
London or New York City
$250k-$300k/yr OnsiteFull Time
2+ YOERequires 2+ years building deep learning systems and strong engineering skills in areas such as CUDA, Triton, Pallas, CuTe DSL, PyTorch, JAX, XLA, CUDA Graphs, FPGA, or ASICs.
CUDA, Triton, Pallas, CuTe DSL, PyTorch, JAX, XLA, CUDA Graphs, FPGA, ASIC
1mo
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Two Sigma Securities, Hardware Engineer
New York City, New York, United States
$165k-$300k/yr HybridFull Time
1+ YOEMinimum 1 year RTL design and verification experience, proficiency in SystemVerilog and Python, FPGA/ASIC knowledge, timing analysis, network protocol familiarity; C++ is a plus.
SystemVerilog, Python, FPGA, ASIC, C++
2w
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Senior Principal FPGA Design Engineer
Manchester or Totowa
OnsiteFull Time
8+ YOERequires 8+ years relevant experience with a bachelor's degree, FPGA or ASIC design, VHDL or Verilog HDL, timing analysis, high-speed interfaces, simulation, scripting, and Secret clearance eligibility.
FPGA, ASIC, VHDL, Verilog HDL, Xilinx Vivado, Intel Quartus, Altera Quartus, Modelsim, Questa, GIT, CVS, Clearcase, Subversion, Perl, Tcl, Python, SERDES, PCIe, DDR2, DDR3, DDR4, LVDS, ADC, DAC
2mo
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FPGA Engineer
Amsterdam or Chicago or London or New York City or Singapore
OnsiteFull Time
Professional FPGA/ASIC design and verification experience; SystemVerilog/Verilog/VHDL and C++; familiarity with EDA tools and scripting (TCL, Python, Bash); university degree in EE/CS/CE or related.
SystemVerilog, Verilog, VHDL, C++, TCL, Python, Bash, EDA
1mo
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RTL Design Engineer
New York City or Palo Alto or London
$205k-$285k/yr HybridFull Time
Production SystemVerilog RTL experience, verification with UVM/cocotb/formal, taped-out silicon, ASIC/SoC design background, simulation and timing collaboration experience.
SystemVerilog, UVM, cocotb, formal, Chipyard, OpenTitan, CVA6, RISC-V
3mo
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Digital Modem Engineer
Austin or Chicago or New York City or London
$150k-$250k/yr OnsiteFull Time
5+ YOE5+ years in digital modem design, modeling, and implementation; strong FPGA/ASIC knowledge; Python/C/C++/Matlab; MS/PhD in EE/CS or equivalent.
Python, C++, C, Matlab
1mo
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FPGA Engineer - Control Systems
Princeton, New Jersey, United States
$150k-$235k/yr OnsiteFull Time
Experienced in FPGA/ASIC digital logic design and verification, RTL and low-latency firmware for multi-domain clock systems; familiarity with Xilinx/AMD RFSoC platforms preferred.
RTL, FPGAs, ASICs, Xilinx, AMD, RFSoC
1w
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Responsible Systems Engineer V, Avionics, Secret clearance
Littleton or Englewood or Littleton or Colorado or Sunnyvale or California or New York City or New Jersey or Denver or Pennsylvania or Connecticut or Dallas or Florida or Grand Prairie or Marietta or Camden or Kentucky or Ocala or Lufkin or Washington
$145k-$270k/yr OnsiteFull Time
8+ YOEBachelor's degree in electrical engineering or related field, 8+ years' experience, avionics systems design and integration expertise, technical leadership, Agile and Model Based Engineering experience, and active DoD Secret clearance.
Model Based Engineering, Agile, Flight Computers, FPGA, ASIC, AI
1mo
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Research Engineer, Chip Design RL (Reinforcement Learning)
San Francisco or New York City
$500k-$850k/yr HybridFull Time
Bachelor's or equivalent, expertise in ASIC/FPGA design and EDA tools, experience with RTL, verification (UVM, formal methods), physical design and tapeout experience; RL experience and tooling experience preferred.
EDA tools, UVM, formal methods, place-and-route
1mo
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Integrated Circuit Design Verification Engineer
Vancouver or Washington or California or New York City
$147k-$259k/yr OnsiteFull Time
10+ YOE10+ years of ASIC design verification experience, BSEE or MSEE (or equivalent), strong UVM/SystemVerilog skills, Siemens Questa experience, scripting (TCL/Make/Perl/Python/Shell), and excellent communication.
UVM, SystemVerilog, Siemens Questa, TCL, Make, Perl, Python, Shell, Linux
2mo
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Senior Network Solution Engineer (Weekend Coverage)
Santa Clara or Westford or Austin or Durham or Redmond or New York
$140k-$270k/yr OnsiteFull Time
5+ YOE5+ years software development (C, C++, Python, or Go) in the networking industry, 5+ years supporting in-field production network equipment, bachelor's degree or equivalent, experience with Linux NIC drivers/ASICs/firmware/network OS, expert Ethernet/IP knowledge.
C, C++, Python, Go, Linux, InfiniBand, NVLink, Spectrum-X
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