16 rtl engineer jobs at 9 companies in Cotati, CA
1mo
Save
Mark Applied
Hide
Senior RTL Engineer, Interconnect Design
San Francisco, California, United States
$225k-$445k/yr HybridFull Time
Senior RTL engineer with deep Verilog/SystemVerilog expertise, SoC interconnect/NoC experience, protocol knowledge (AXI, APB, CXL, PCIe, Ethernet), RTL signoff flows, and track record from microarchitecture through tape-out.
Verilog, SystemVerilog, AXI, APB, CXL, PCIe, Ethernet, RDMA, RoCE, network-on-chip, NoC, FPGA, lint, CDC/RDC, synthesis, formal verification, static timing analysis, power analysis, design-for-test
3mo
Save
Mark Applied
Hide
ASIC Design Engineer - Pixel IP DMA
Sunnyvale or San Francisco
OnsiteFull Time
10+ YOEBachelor's degree with 10 years experience in front-end ASIC RTL design; strong collaboration and communication skills; experience with DMA engines, memory controllers, interconnects, and AMBA protocols.
RTL, Synthesis, AMBA (AXI, AHB, APB)
3w
Save
Mark Applied
Hide
Wireless Design Verification Engineer
San Francisco, California, United States
OnsiteFull Time
Join a wireless system-on-chip team to drive energy-efficient silicon design, verification, emulation, and cross-discipline integration across RF/Analog, Systems/PHY/MAC, VLSI/RTL, and FW/SW domains.
VLSI, RTL, Emulation
1mo
Save
Mark Applied
Hide
Hardware Engineer - FPGA
Milpitas or San Francisco
$152k-$222k/yr OnsiteFull Time
7+ YOEExperienced FPGA/ASIC engineer with RTL (Verilog/SystemVerilog) skills, FPGA tool experience, 7+ years (BS) or 4+ years (MS), verification experience (UVM/VMM) preferred.
Verilog, SystemVerilog, UVM, VMM
3d
Save
Mark Applied
Hide
Software Engineer, Silicon Design Methodology
San Francisco, California, United States
$225k-$380k/yr HybridFull Time
Strong software engineering in C++, Python, Rust, or similar systems languages; experience with engineering infrastructure, developer tools, EDA/CAD, compilers, verification, RTL/IP integration, and digital design.
C++, Python, Rust, EDA, CAD, RTL, IP, SoC
1mo
Save
Mark Applied
Hide
FPGA Engineer
El Segundo or Los Angeles or Washington or San Francisco or Seattle or London
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor's in a relevant field, 5+ years FPGA RTL design experience, Verilog/SystemVerilog, AXI protocols, Vivado and SoC FPGA experience, Bash/Python scripting, U.S. Person required.
Verilog, SystemVerilog, AXI4, AXI4-Lite, AXI4-Stream, Vivado Design Suite, Zynq, Ultrascale, Ultrascale+, Versal, TCP, UDP, IP, I2C, JTAG, UART, SPI, CAN, Bash, Python, Simulink, MATLAB, C, C++, SystemC, Chisel, VHDL, git, Bitbucket CI, Jenkins
1mo
Save
Mark Applied
Hide
Firmware Engineer
El Segundo or Los Angeles or Washington or San Francisco or Seattle or London
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor's in CE/EE/CS, 5+ years FPGA RTL design experience, Verilog/SystemVerilog, AXI protocols, Vivado/SoC FPGAs, TCP/UDP/IP and serial protocols, Bash/Python scripting; U.S. Person required.
Verilog, SystemVerilog, Vivado Design Suite, Simulink, MATLAB, C, C++, SystemC, Chisel, VHDL, Bash, Python, git, Bitbucket CI, Jenkins
1mo
Save
Mark Applied
Hide
Design Verification Engineer
San Francisco, California, United States
OnsiteFull Time
Digital-focused design verification for pre-silicon IP: DV methodology, test-plan and verification environment development, test writing, debug, coverage, and RTL sign-off for tape-out.
3w
Save
Mark Applied
Hide
Research Engineer, Chip Design RL (Reinforcement Learning)
San Francisco or New York City
$500k-$850k/yr HybridFull Time
Bachelor's or equivalent, expertise in ASIC/FPGA design and EDA tools, experience with RTL, verification (UVM, formal methods), physical design and tapeout experience; RL experience and tooling experience preferred.
EDA tools, UVM, formal methods, place-and-route
2mo
Save
Mark Applied
Hide
Mixed-Signal Verification Engineer
San Francisco Bay Area or San Diego
OnsiteFull Time
10+ YOEBS with 10+ years in RF/mixed-signal verification; SystemVerilog/UVM experience; HDL (SystemVerilog/Verilog); Python/Matlab a plus; familiarity with analog/RF blocks; VLSI/RTL integration.
SystemVerilog, Verilog, UVM, Python, Matlab, Virtuoso, ADE, HED
6d
Save
Mark Applied
Hide
Core Performance Architect
Santa Clara or Hsinchu or Austin or Berkeley
$179k-$219k/yr OnsiteFull Time
3+ YOEMS in Computer Science/Computer Architecture,3+ years in high-performance processor development,experience with RTL/FPGA and performance analysis,ability to deliver HW/SW products.
RTL, FPGA, Integrated Logic Analyzer
6d
Save
Mark Applied
Hide
Core Performance Architect
Santa Clara or Hsinchu or Austin or Berkeley
$179k-$219k/yr OnsiteFull Time
3+ YOEMS in Computer Science or Computer Architecture, 3+ years in high-performance processor development, hands-on RTL/FPGA experience, EM/FPGA debug, performance analysis, strong communication and leadership.
RISC-V, RTL, FPGA, Integrated Logic Analyzer, FPGA flows
6d
Save
Mark Applied
Hide
Core Performance Architect
Santa Clara or Hsinchu or Austin or Berkeley
$159k-$194k/yr OnsiteFull Time
1+ YOEMS in Computer Science/Computer Architecture,1+ year high-performance processor development experience,hands-on RTL/FPGA expertise,EMR not applicable; analyze micro-architecture and workload bottlenecks.
RTL, FPGA, Integrated Logic Analyzer, verification/validation
3w
Save
Mark Applied
Hide
Director, Product Engineering Practice Specialist (Semiconductor)
San Francisco or Austin
$200k-$280k/yr OnsiteFull Time
15+ YOE15+ years in semiconductor/product engineering with deep expertise in silicon, SoC, RTL, verification, validation, embedded software, solutioning, and client advisory for large-scale engineering transformations.
Synopsys, Cadence, Siemens, UVM, SystemVerilog, Linux, C++, RISC-V
1mo
Save
Mark Applied
Hide
Member of Technical Staff - Low Level & Kernels Capabilities
San Francisco or Toronto or Seattle
$200k-$350k/yr OnsiteFull Time
Experienced low-level systems engineer fluent in C/C++/CUDA and Python, kernel and kernel-optimization experience, hardware-aware coding, familiarity with LLMs, and ability to design robust, ungameable RL environments.
C, C++, CUDA, Python, assembly, cuBLAS, FFTW, OpenSSL, FPGA, RISC-V, SIMD, AVX, TPU, RTL, HDL, HLS, MLIR, LLVM, Mojo, Triton, gem5, Lean, Coq, SMT
3d
Save
Mark Applied
Hide
Senior Consultant
San Francisco, California, United States
OnsiteFull Time
5+ YOERequires 5–20 years in hardware-assisted verification, Linux boot and kernel debugging, digital design, emulation, PCIe Gen6, Python, C or Perl scripting, and SystemVerilog RTL coding.
AI, High Performance Computing (HPC), SystemVerilog, Linux, PCIe, HBM, JTAG, UART, Virtual IXIA, ZeBu, Palladium, Veloce, HAPS, Protium, ProFPGA, Python, C, Perl, UVM, C++, SystemC, PCIe Gen6, QEMU
Explore Jobs