88 rtl engineer jobs at 38 companies in Fairfax, CA
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RTL Engineer
Mountain View, California, United States
$250k-$375k/yr OnsiteFull Time
5+ YOE5+ years RTL/SoC design to silicon, expert Verilog/SystemVerilog, synthesis/timing/CDC/SDC awareness, microarchitecture skills, collaboration across DV/PD/DFT, and scripting in Python/Tcl.
SystemVerilog, Verilog, Python, Tcl, SDC, STA, UPF, HBM, PCIe, SerDes, RISC-V, FPGA
2mo
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Senior RTL Engineer, Interconnect Design
San Francisco, California, United States
$225k-$445k/yr HybridFull Time
Senior RTL engineer with deep Verilog/SystemVerilog expertise, SoC interconnect/NoC experience, protocol knowledge (AXI, APB, CXL, PCIe, Ethernet), RTL signoff flows, and track record from microarchitecture through tape-out.
Verilog, SystemVerilog, AXI, APB, CXL, PCIe, Ethernet, RDMA, RoCE, network-on-chip, NoC, FPGA, lint, CDC/RDC, synthesis, formal verification, static timing analysis, power analysis, design-for-test
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RTL Design Engineer
New York City or Palo Alto or London
$205k-$285k/yr HybridFull Time
Production SystemVerilog RTL experience, verification with UVM/cocotb/formal, taped-out silicon, ASIC/SoC design background, simulation and timing collaboration experience.
SystemVerilog, UVM, cocotb, formal, Chipyard, OpenTitan, CVA6, RISC-V
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Senior CPU RTL Design Engineer
Mountain View, California, United States
$163k-$237k/yr OnsiteFull Time
8+ YOEBachelor's degree or equivalent,8+ years implementing CPU cache subsystems,RTL/System Verilog experience,and familiarity with lint and UPF; strong microarchitecture and collaboration skills.
System Verilog, Lint, UPF, ARM Instruction Set Architecture
2w
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Staff SoC RTL Engineer
Burlingame, California, United States
$175k-$230k/yr HybridFull Time
5+ YOEBS, MS, or Ph.D. in electrical or computer engineering; 5+ years of SoC/ASIC front-end design and integration; SystemVerilog or Verilog; computer architecture, low-power design, subsystem, and VCS experience.
SystemVerilog, Verilog, VCS, C++, FPGA
3mo
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Member of Technical Staff, Hardware, RTL Design Engineer
Palo Alto or Austin
$200k-$420k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE and 5+ years industry experience with advanced process nodes (7nm or below); strong RTL, synthesis, physical design, and timing tool experience; expertise in computer architecture and silicon delivery.
System Verilog, VCS, Verdi, Fusion Compiler, PrimeTime, C, C++, python, ISA assembly, PCIe, UCIe, HBM, DDR, AXI, CHI, Static Timing Analysis (STA)
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Micro-Architect and RTL Designer
Mountain View, California, United States
$120k-$600k/yr HybridFull Time
4+ YOE4+ years micro-architecture and RTL design experience; SystemVerilog, Python, C/C++; ASIC/SoC concept-to-silicon experience; synthesis and sign-off flows; verification collaboration; US work authorization and export-control compliance.
SystemVerilog, Python, C/C++
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Hardware Design Engineer
Tempe or San Jose or San Francisco or New York City
$133k-$210k/yr OnsiteFull Time
4+ YOEBachelor's degree or equivalent in electrical or computer engineering, 4+ years in high-speed digital board design and FPGA/RTL development, US citizenship, Secret clearance eligibility, and up to 10% travel.
SystemVerilog, Verilog, VHDL, AMD Vivado, Intel Quartus, Synopsys Synplify, Mentor Xpedition, Cadence, Altium, HyperLynx, Python, TCL, Perl, ModelSim, Questa, Git, Claude Code, Copilot, DDR4, SERDES, UART, I2C, SPI, LVDS, FPGA, RTL, SoC, ADC, DAC, CI/CD, AI
3mo
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ASIC Design Engineer - Pixel IP DMA
Sunnyvale or San Francisco
OnsiteFull Time
10+ YOEBachelor's degree with 10 years experience in front-end ASIC RTL design; strong collaboration and communication skills; experience with DMA engines, memory controllers, interconnects, and AMBA protocols.
RTL, Synthesis, AMBA (AXI, AHB, APB)
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AI Silicon, Digital Design Engineer
Palo Alto, California, United States
OnsiteFull Time
8+ YOEB.S. or M.S. in EE/Computer Engineering, 8+ years ASIC/SoC digital design experience, Verilog RTL expertise, EDA tool proficiency, synthesis/timing/LEC experience, and mentorship/communication skills.
Verilog, RTL, EDA tools, Logical Equivalence Checking (LEC), Clock Domain Crossing (CDC), Reset Domain Crossing (RDC)
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Staff Silicon Validation Engineer
Palo Alto, California, United States
$186k-$232k/yr OnsiteFull Time
Bachelor's degree in EE/CSE or related, proficiency in C/C++, Python and Linux shell, experience with SoC/FPGA validation preferred (AMD Petalinux, RTL), strong analytical and communication skills.
C, C++, Python, Linux shell, AMD Petalinux, FPGA, RTL
1w
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Software Engineer - FPGA-Accelerated RTL Simulation
Berkeley, California, United States
$179k-$219k/yr OnsiteFull Time
7+ YOEBS, MS, or PhD in CS, CE, or EE; 7+ years building complete modern C++ applications; strong C++ concurrency and multithreaded application experience; strong oral and written communication.
C++, C++20, Chisel, Xilinx FPGAs, MLIR, CIRCT, LLVM, RISC-V, FireSim
4d
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Principal Verification Engineer
Mountain View or Redmond or Hillsboro or Austin or Raleigh
$143k-$275k/yr HybridFull Time
3+ YOERequires a degree in electrical engineering, computer engineering, computer science, or related field and 3–8+ years of technical engineering experience depending on degree; verification, UVM, RTL, simulation, scripting, and security screening required.
Universal Verification Methodology (UVM), C, Zsh, Bash, Python, Perl, Verilog, Microsoft Azure, AXI, AMBA
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Senior DFT Engineer
Saratoga, California, United States
$120k-$220k/yr OnsiteFull Time
8+ YOESenior DFT Engineer with 8+ years in design-for-test for complex digital ASICs/SoCs; expertise with DFT tools; RTL/ASIC test optimization.
Verilog, SystemVerilog, UVM, VHDL, Tcl, Python, Perl, Synopsys DFT Compiler, Tessent, DFTMAX, MBIST, JTAG, ATPG
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Hardware Engineer - FPGA
Milpitas or San Francisco
$152k-$222k/yr OnsiteFull Time
7+ YOEExperienced FPGA/ASIC engineer with RTL (Verilog/SystemVerilog) skills, FPGA tool experience, 7+ years (BS) or 4+ years (MS), verification experience (UVM/VMM) preferred.
Verilog, SystemVerilog, UVM, VMM
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Design Engineer III
Menlo Park or Sunnyvale
$140k-$150k/yr HybridFull Time
5+ YOERequires a BS in electrical/computer engineering or computer science, 5+ years of experience, SystemVerilog/UVM verification, coverage and SVA, RTL debug, simulators, Python or Perl, and digital design fundamentals.
SystemVerilog, UVM, VCS, Xcelium, Questa, Verdi, Python, Perl, PrimeTime PX (PTPX), PrimePower, UPF, Palladium, Zebu, RTL-to-GDSII
4d
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Senior Digital Design Engineer
Vancouver or Chandler or San Francisco
$150k-$200k/yr HybridFull Time
6+ YOEBachelor's or master's degree in electrical or computer engineering, 6+ years of digital IC design experience, and hands-on Verilog or SystemVerilog RTL development for complex SoCs or ASICs.
Verilog, SystemVerilog, Synopsys, Cadence, SDC, UPF, CPF
4d
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ASIC Design Engineer
Alameda, California, United States
$100k-$140k/yr OnsiteFull Time
Bachelor's in Electrical Engineering or Computer Science with ASIC industry experience, or Master's/PhD with hands-on ASIC experience. Requires analog and RTL design, programming, testing, debugging, communication, and Linux experience.
Linux, SPI, I2C, Cadence, Raspberry Pi, PDKs
3w
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Hardware Engineer
Colorado Springs or Irvine or Longmont or Fremont or Rochester or San Jose
$91k-$113k/yr OnsiteFull Time
Early-career candidates pursuing or recently completing an engineering degree; familiarity with hardware, firmware, ASIC/SoC, or systems; programming and design experience through coursework or projects; strong analytical and communication skills.
Verilog/SystemVerilog, RTL, FPGA, C, C++, Assembly, Python, Java, Go, SQL, JavaScript, Git, Linux, IDE, CAD, Microsoft Office, RTOS
2mo
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FPGA Engineer
El Segundo or Los Angeles or Washington or San Francisco or Seattle or London
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor's in a relevant field, 5+ years FPGA RTL design experience, Verilog/SystemVerilog, AXI protocols, Vivado and SoC FPGA experience, Bash/Python scripting, U.S. Person required.
Verilog, SystemVerilog, AXI4, AXI4-Lite, AXI4-Stream, Vivado Design Suite, Zynq, Ultrascale, Ultrascale+, Versal, TCP, UDP, IP, I2C, JTAG, UART, SPI, CAN, Bash, Python, Simulink, MATLAB, C, C++, SystemC, Chisel, VHDL, git, Bitbucket CI, Jenkins
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