82 asic engineer jobs at 35 companies in Fairfax, CA
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ASIC Design Engineer
Alameda, California, United States
$100k-$140k/yr OnsiteFull Time
Bachelor's in Electrical Engineering or Computer Science with ASIC industry experience, or Master's/PhD with hands-on ASIC experience. Requires analog and RTL design, programming, testing, debugging, communication, and Linux experience.
Linux, SPI, I2C, Cadence, Raspberry Pi, PDKs
3w
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ASIC Engineer, EDA Infrastructure
Sunnyvale or Menlo Park
$114k-$172k/yr OnsiteFull Time
5+ YOEBachelor's in CS/CE or equivalent, 5+ years with EDA tools and scripting (Python, Tcl), SystemVerilog/HDL experience, ASIC EDA infrastructure management, and cross-team/vendor communication.
SystemVerilog, Python, Tcl, EDA
1w
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ML ASIC Design Engineer
Mountain View or New York City
$175k-$215k/yr HybridFull Time
5+ YOEBS in Computer Engineering or equivalent experience; 5+ years with SystemVerilog, ASIC RTL design, and microarchitecture; 3+ years designing high-performance CPU, GPU, or NPU cores; Python or C++.
SystemVerilog, Python, C++, Chisel, Scala
3mo
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ASIC Design Engineer - Pixel IP DMA
Sunnyvale or San Francisco
OnsiteFull Time
10+ YOEBachelor's degree with 10 years experience in front-end ASIC RTL design; strong collaboration and communication skills; experience with DMA engines, memory controllers, interconnects, and AMBA protocols.
RTL, Synthesis, AMBA (AXI, AHB, APB)
2w
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ASIC/SOC DFT Engineer (Silicon Engineering)
Palo Alto, California, United States
$135k-$210k/yr OnsiteFull Time
1+ YOEBachelor's degree in electrical engineering, computer engineering, or computer science; 1+ year ASIC experience; scan insertion or DFT setup experience; scripting and Verilog/SystemVerilog familiarity preferred.
csh, Bash, Perl, Python, Verilog, SystemVerilog, UPF
2mo
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ASIC Design Engineer (eInfochips)
Mountain View, California, United States
OnsiteFull Time
5+ YOE5+ years Verilog/SystemVerilog design; Fusion Compiler experience; scripting; PCIe and AXI interfaces; ARM Fabric IP; IPXACT; EDA tools.
Fusion Compiler, VCS, Questa CDC, Spyglass Lint, Design Compiler, Genus, UPF, Python, Tcl, Perl, Verilog, SystemVerilog, AXI, AMBA, IPXACT
1mo
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Senior ASIC DFT Engineer, Silicon
Mountain View, California, United States
$163k-$237k/yr OnsiteFull Time
8+ YOE8+ years DFT experience, Bachelor in EE or related, Ohio? (not applicable). Proficiency with DFT EDA tools, ATPG/scan/MBIST/GLS, Perl or Python, strong communication and critical thinking.
Tessent, Genus, Fusion Compiler (FC), Simvision, Spyglass-DFT, Siemens Tessent, Perl, Python
3mo
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Software Engineer, ASIC
Austin or South San Francisco
$123k-$216k/yr OnsiteFull Time
Bachelor's degree in computer science or related field; experience with EDA compute environments; proficiency in Rust/Go/C++; Linux storage and datacenter systems; multi-cloud/hybrid deployments; embedded cross-compilation toolchains.
Rust, Python, Go, Cadence, Terraform, Ansible, Packer, MAAS, Bazel, Nix, Prometheus, ClickHouse, Grafana, Ray, Docker, Kubernetes, AWS, OCI, RHEL, Ubuntu
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ASIC Package SI/PI Engineer
San Francisco, California, United States
$266k-$445k/yr HybridFull Time
5+ YOERequires 5+ years in signal integrity, power integrity, high-speed interconnects, PDN, and package electrical design, plus SI/PI simulation, package layout, and automated optimization experience.
Synopsys HSPICE, Ansys EDT, HFSS-PI, SIwave, Cadence Clarity, Sigrity PowerSI, Sigrity PowerDC, Cadence APD/SIP, VNA, TDR/TDT
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Senior Design Engineer
Mountain View or Redmond
$120k-$235k/yr HybridFull Time
5+ YOERequires a doctorate plus 1+ year, master's plus 4+ years, bachelor's plus 5+ years, or equivalent experience in electrical, computer, or related engineering. Preferred expertise includes digital design, RTL, NoC, ASIC/SoC, synthesis, and post-silicon debug.
Intellectual Property (IP), Register Transfer Level (RTL), System on Chip (SOC), Verilog, SystemVerilog, Clock Domain Crossing (CDC), NoCs, ASIC, CPU
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Senior DFT Engineer
Saratoga, California, United States
$120k-$220k/yr OnsiteFull Time
8+ YOESenior DFT Engineer with 8+ years in design-for-test for complex digital ASICs/SoCs; expertise with DFT tools; RTL/ASIC test optimization.
Verilog, SystemVerilog, UVM, VHDL, Tcl, Python, Perl, Synopsys DFT Compiler, Tessent, DFTMAX, MBIST, JTAG, ATPG
3w
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Hardware Engineer
Colorado Springs or Irvine or Longmont or Fremont or Rochester or San Jose
$91k-$113k/yr OnsiteFull Time
Early-career candidates pursuing or recently completing an engineering degree; familiarity with hardware, firmware, ASIC/SoC, or systems; programming and design experience through coursework or projects; strong analytical and communication skills.
Verilog/SystemVerilog, RTL, FPGA, C, C++, Assembly, Python, Java, Go, SQL, JavaScript, Git, Linux, IDE, CAD, Microsoft Office, RTOS
1mo
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Hardware Engineer - FPGA
Milpitas or San Francisco
$152k-$222k/yr OnsiteFull Time
7+ YOEExperienced FPGA/ASIC engineer with RTL (Verilog/SystemVerilog) skills, FPGA tool experience, 7+ years (BS) or 4+ years (MS), verification experience (UVM/VMM) preferred.
Verilog, SystemVerilog, UVM, VMM
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Senior Digital Design Engineer
Vancouver or Chandler or San Francisco
$150k-$200k/yr HybridFull Time
6+ YOEBachelor's or master's degree in electrical or computer engineering, 6+ years of digital IC design experience, and hands-on Verilog or SystemVerilog RTL development for complex SoCs or ASICs.
Verilog, SystemVerilog, Synopsys, Cadence, SDC, UPF, CPF
1mo
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Lead SoC Design Engineer
Los Altos, California, United States
OnsiteFull Time
Anodize: Developing next-generation personal computing hardware and consumer electronics.
10+ YOE10+ years developing complex ASICs; Bachelor's in EE/CE (or equivalent); deep knowledge of AMBA protocols, Verilog/SystemVerilog/SVA, SDC timing constraints, multi-power-domain design and UPF; experience with ASIC CAD flows.
AMBA AXI, AXI-S, APB, Verilog, SystemVerilog, SystemVerilog Assertions (SVA), SDC, STA, Lint, CDC, RDC, LEC, UPF, UCIe, DDR, Arm
2w
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Staff SoC RTL Engineer
Burlingame, California, United States
$175k-$230k/yr HybridFull Time
5+ YOEBS, MS, or Ph.D. in electrical or computer engineering; 5+ years of SoC/ASIC front-end design and integration; SystemVerilog or Verilog; computer architecture, low-power design, subsystem, and VCS experience.
SystemVerilog, Verilog, VCS, C++, FPGA
2mo
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Inference Optimization Engineer
Los Altos or United States or Canada
$198k-$286k/yr HybridFull Time
5+ YOE5+ years in distributed systems or performance engineering; experience building reusable tooling; strong technical judgment, communication, and leadership; GPU/kernel, inference engine, Kubernetes, and LLM familiarity helpful.
GPU, ASIC, inference engine, Kubernetes, Modular Cloud, LLM architectures
1mo
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AI Silicon, Digital Design Engineer
Palo Alto, California, United States
OnsiteFull Time
8+ YOEB.S. or M.S. in EE/Computer Engineering, 8+ years ASIC/SoC digital design experience, Verilog RTL expertise, EDA tool proficiency, synthesis/timing/LEC experience, and mentorship/communication skills.
Verilog, RTL, EDA tools, Logical Equivalence Checking (LEC), Clock Domain Crossing (CDC), Reset Domain Crossing (RDC)
2w
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Chip Firmware Validation Engineer
Mountain View, California, United States
$185k-$245k/yr HybridFull Time
5+ YOEBachelor's degree in electrical engineering, computer science, or related field; 5+ years of ASIC firmware validation; embedded software, Linux, hardware-software integration, Git, CMake, Python, C, C++, and MongoDB experience.
GDB, JTAG, logic analyzers, Linux, Git, CMake, Python, C, C++, MongoDB, Snowflake, CMIS, OpenBMC
1mo
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RTL Design Engineer
New York City or Palo Alto or London
$205k-$285k/yr HybridFull Time
Production SystemVerilog RTL experience, verification with UVM/cocotb/formal, taped-out silicon, ASIC/SoC design background, simulation and timing collaboration experience.
SystemVerilog, UVM, cocotb, formal, Chipyard, OpenTitan, CVA6, RISC-V
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