3mo
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RTL Design Engineer
Beaverton, Oregon, United States
OnsiteFull Time
Bachelor's degree in Electrical Engineering; experience with RTL design and Verilog/SystemVerilog preferred.
Verilog, SystemVerilog, Python, Perl
2mo
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Principal PCIe CXL RTL Design Engineer
Aix-en-Provence or Sofia or Hillsboro or Bangalore
HybridFull Time
5+ YOE5+ years RTL design experience; expertise in Verilog/System Verilog; Master’s degree or PhD in Electrical or Computer Engineering (or equivalent); knowledge of PCIe/CXL/AMBA; FPGA prototyping; strong English and collaboration skills.
System Verilog, Verilog, PCIe, CXL, AMBA, FPGAs
22h
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Senior Memory Controller RTL Design Engineer
Redmond or Mountain View or Raleigh or Austin or Hillsboro
$120k-$235k/yr HybridFull Time
1+ YOEDegree in EE/CE/CS or equivalent with 1–5+ years experience depending on degree, strong Verilog/SystemVerilog RTL design skills, DDR4/DDR5 controller experience preferred, scripting (Perl/Tcl/Python), familiarity with front-end verification and low-power/timing checks, ability to pass Microsoft security and export control screenings.
Verilog, System Verilog, Perl, Tcl, Python
1mo
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Sr. CPU RTL Front End Methodology Engineer
Austin or Phoenix or Hillsboro
$164k-$312k/yr OnsiteFull Time
6+ YOE5+ MgmtRequires 6+ years silicon CPU logic experience, 5+ years technical leadership; degree in CS/Electrical/Electronics engineering (or related) with substantial experience; experience with RTL methodologies, front-end and back-end flows, and use of AI tools.
AI tools
2d
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CPU Design Methodology Engineer
Hillsboro or Austin or Santa Clara or Arizona
$136k-$265k/yr OnsiteFull Time
5+ YOEMasters in Computer or Electrical Engineering or equivalent,5+ years chip/SOC design experience,RTL/verification and design automation expertise,proficient in scripting (Perl/Python),strong analytical and interpersonal skills.
Verilog, UVM, System Verilog, Perl, Python
2d
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CPU Design Methodology Engineer
Hillsboro or Austin or Santa Clara or United States
$136k-$265k/yr HybridFull Time
5+ YOEMasters in Computer/Electrical Engineering or equivalent experience,5+ years chip/SOC design experience,RTL (Verilog),UVM/System Verilog,design automation,Perl/Python skills,analytical and interpersonal skills.
Verilog, UVM, System Verilog, Perl, Python
4d
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Senior FPGA Design Engineer (Nextest, Tualatin, OR)
Tualatin or San Jose
$170k-$273k/yr OnsiteFull Time
8+ YOEB.S. or M.S. in electrical engineering,8+ years relevant experience,RTL/Verilog,Intel/Xilinx tool flows,static timing analysis,FPGA transceivers,EM simulation lab validation,C/C++,Linux/Windows proficiency.
C, C++, Verilog HDL, Intel/Xilinx FPGA tool flows, UVM, Linux, Windows, oscilloscope, power supply, waveform generator, ATE
1mo
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Sr. Digital ASIC Engineer (Hillsboro, OR, US)
Hillsboro, Oregon, United States
$91k-$177k/yr OnsiteFull Time
5+ YOEExperienced digital design engineer with RTL/Verilog/System Verilog skills, SOC/low-power design, MATLAB/Python/C modeling, FPGA prototyping, and silicon bring-up; typically 5+ years (BSEE) or 3+ (MSEE) industry experience.
Verilog, System Verilog, MATLAB, Python, C, Perl, Tcl, Makefiles, Shell scripts, FPGA, Oscilloscope, Logic Analyzer, Spectrum Analyzer
1w
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Senior CPU Performance Architect
Austin or Portland or Mountain View or Poughkeepsie
$163k-$237k/yr OnsiteFull Time
8+ YOE8+ years in microprocessor architecture and performance, Bachelor's in EE/CE/CS or equivalent, RN? (ignore) BLS? (ignore) Experience with performance modeling, EM/RTL correlation, and system software knowledge.
ARM, RISC-V, x86, RTL, Linux
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