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RTL integration Engineer
San Jose, California, United States
$144k-$230k/yr OnsiteFull Time
12+ YOEBachelor's plus 12+ years experience; deep RTL, UVM/SystemVerilog, synthesis, timing, CDC/RDC, GLS, SDF simulations, NCSim/VCS, Palladium modeling, STA, and strong debugging and communication skills.
RTL, UVM, SystemVerilog, SDF, NCSim, VCS, Palladium
2mo
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SoC RTL Design Engineer
San Jose or Bangalore
HybridFull Time
8+ YOEBS/MS in Electrical or Computer Engineering; 8+ years in digital IC design with chip infrastructure ownership (clocking, power management, reset/DFT) at block-lead or subsystem level; strong SystemVerilog and infrastructure RTL skills; experience with embedded microcontroller integration and security features.
SystemVerilog, RTL Design, Power Management, Clock Gating, Reset, DFT, BIST, Interrupt Controller, UART, JTAG, PCIe, UCIe
2mo
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Sr. Engineer, RTL Implementation
Austin or Santa Clara
$100k-$500k/yr HybridFull Time
Experienced in high-performance physical design; RTL coding (Verilog/VHDL); synthesis/place-and-run; CPU micro-architecture.
Verilog, VHDL, Synthesis tools, Place and Route tools
2mo
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Senior Engineer, RTL Design
San Jose, California, United States
$138k-$206k/yr OnsiteFull Time
5+ YOEBS with 5 years RTL development or MS with 3 years; PhD in Computer/Electrical Engineering; HDL/Verilog; FPGA; PCIe/CXL/NVMe; CAD tools.
Verilog, HDL, CAD tools, Synopsys, Mentor, Cadence, FPGA, PCIe, CXL, NVMe, AXI, DDR4/5, Ethernet
1mo
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Senior Engineer, GPU RTL Design
Austin or San Jose
$124k-$208k/yr OnsiteFull Time
4+ YOEMaster’s in Electrical/Computer Engineering required for senior/staff; Senior requires 4+ years. Requires RTL design experience (Verilog/SystemVerilog), ASIC front-end flow familiarity, microarchitecture knowledge, and ability to access export-controlled information.
Verilog, SystemVerilog
4d
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CPU Microarchitect/RTL Engineer - Fetch, Out of Order
Santa Clara, California, United States
OnsiteFull Time
Experienced engineer to drive CPU front-end and out-of-order microarchitecture and RTL development for high-performance, low-power cores.
1mo
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Staff RTL Design Engineer - CPU LS/PF/MMU
Santa Clara or Austin
$179k-$219k/yr OnsiteFull Time
3+ YOEBS/MS in CS/CE/EE or equivalent, 3+ years design experience, CPU RTL design experience, proficiency in Verilog/System Verilog/VHDL, strong software engineering (OOP, functional, TDD), verification skills (SVA, coverage).
Chisel, FIRRTL, Verilog, System Verilog, VHDL, Scala, Bluespec, RISC-V, Git/Github, Jira, Confluence, SVA
1w
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RTL Power Optimization Engineer – New College Grad 2026
Santa Clara, California, United States
$116k-$219k/yr OnsiteFull Time
MS or PhD in EE/CE (pursuing or recent); understanding of RTL low-power design, backend flows, power analysis tools; Python and ML experience; strong communication and RTL debugging skills.
PowerArtist, PrimeTime PX, Python, Verilog
1mo
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RTL Design and Architect lead
San Jose or Austin
OnsiteFull Time
10+ YOE10+ years industry experience, Bachelor's/Master's in Electronics/Electrical Engineering, SOC project leadership, RTL design with VHDL/Verilog/SystemVerilog, strong digital design fundamentals, exposure to micro-processor integration and high-speed peripherals, Python familiarity.
VHDL, Verilog, SystemVerilog, Python, GDSII, DDR, PCIe, UCIe, Ethernet
1mo
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RTL/Logic Design Engineer
Santa Clara or United States
$166k-$250k/yr HybridFull Time
5+ YOE5+ years digital design experience; expertise in RTL/Verilog, high-speed memory interfaces (HBM, GDDR); familiarity with Synopsys, Cadence, Mentor Graphics; strong simulation, synthesis, timing analysis skills; BS/MS in engineering.
Verilog, Synopsys, Cadence, Mentor Graphics, Register Transfer Level (RTL)
2mo
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Senior Principal Engineer, Micro-architecture and RTL
Santa Clara, California, United States
$182k-$273k/yr OnsiteFull Time
15+ YOEBachelor's in CS/EE with 15+ yrs; MS with 10-12 yrs; PhD with 8-10 yrs. SystemVerilog RTL, UVM, Ethernet, PCIe, CXL experience; leadership ability.
SystemVerilog, SystemVerilog Assertions, Universal Verification Methodology, RTL, PCIe, CXL, Ethernet
1w
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Digital IC Design Engineer | BCP
Santa Clara, California, United States
$130k-$241k/yr OnsiteFull Time
3+ YOEB.S. in Electrical Engineering, 3+ years digital design experience; RTL/Verilog/SystemVerilog, Cadence, Python, UVM, and GDSII experience preferred; ability to implement and verify synthesizable RTL to GDSII.
RTL, Verilog/Systemverilog, Cadence, Python, UVM, VAMS, GDSII
2mo
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Staff Design Engineer
San Jose, California, United States
$145k-$246k/yr OnsiteFull Time
7+ YOEBachelor's in Computer or Electrical Engineering; 7+ years digital circuit design; RTL and gate-level verification; collaboration across multi-functional teams.
RTL, Verilog, Gate-level verification
1mo
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Product Development Engineer
San Jose, California, United States
$106k-$154k/yr OnsiteFull Time
5+ YOEBachelor's or Master's in Electrical Engineering (or related) with 5+ years industry experience in IC design/test, DFT/ATPG/MBIST/IJTAG/JTAG, RTL design/synthesis/verification, scripting (Python/Perl/TCL), and semiconductor manufacturing test.
Python, Perl, TCL, ATPG, MBIST, IJTAG, JTAG, RTL, Secure Device Manager (SDM)
1w
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IP Design Verification Engineer
Santa Clara, California, United States
$164k-$269k/yr HybridFull Time
6+ YOEBachelor's degree or equivalent with 6+ years (less with advanced degree), proficiency in System Verilog and RTL, testbench and verification environment experience, strong debugging and problem-solving skills.
System Verilog, RTL
1mo
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Embedded Hardware Engineer
San Jose or Pittsburgh
$160k-$210k/yr OnsiteFull Time
8+ YOE8+ years PCB design and embedded software experience, 5+ years C/C++, experience with silicon bring-up, board bring-up, boot ROM/firmware, RTL/FPGA validation, and embedded platforms (MSP430, STM32, Ambiq Apollo, PIC32).
C, C++, MSP430, STM32, Ambiq Apollo, PIC32, Altium Develop, RTL simulators, FPGA emulators
1mo
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Senior Engineer, Digital Design Engineering
San Jose, California, United States
$157k-$202k/yr HybridFull Time
2+ YOEMaster's in EE/CE/CS or related, 2+ years digital/mixed-signal design and verification experience, expertise in RTL, Lint, CDC, Verilog/System Verilog, Cadence or Synopsis tools, simulation, synthesis, and ASIC flow.
Cadence, Synopsis, Verilog, System Verilog, RTL, Lint, CDC
2w
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3D Stacked DRAM-on-Logic Design Engineer
San Jose, California, United States
$150k-$260k/yr OnsiteFull Time
5+ YOEBachelor's in EE,5+ years experience in digital IP/SoC and RTL design for 3D-stacked DRAM,experience with Verilog/VHDL,memory controllers,BIST/DFT/DFD,and strong English communication.
Verilog, VHDL, RTL
2mo
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Digital Design Engineer - New College Grad
San Jose, California, United States
$99k-$183k/yr HybridFull Time
Master's degree in EE or related field; experience with RTL coding, Verilog models, and analog/digital design; test support and chip bring-up; strong communication and team skills.
Verilog, RTL, Simulations, I2C, SPI, AHB, APB, Bench testing, ATE testing
3w
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Hardware Engineer - FPGA
Milpitas or San Francisco
$152k-$222k/yr OnsiteFull Time
7+ YOEExperienced FPGA/ASIC engineer with RTL (Verilog/SystemVerilog) skills, FPGA tool experience, 7+ years (BS) or 4+ years (MS), verification experience (UVM/VMM) preferred.
Verilog, SystemVerilog, UVM, VMM
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