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Sr. Engineer, ASIC Design
San Jose, California, United States
$160k-$192k/yr OnsiteFull Time
1+ YOEBS or MS in Electrical/Computer Engineering; 1+ years ASIC design; Verilog; ASIC verification tools; scripting; ability to work independently.
Verilog, Xcelium, VCS, Questa, Python, C, C++
1w
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Senior ASIC Design Engineer
Santa Clara or Durham
$168k-$311k/yr OnsiteFull Time
8+ YOEMasters in EE/CE (or equivalent),8+ years ASIC design experience,micro-architecture and RTL in Verilog,ASIC flow knowledge,EMR not applicable.
Verilog, Python, Perl, C, C++
2w
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ASIC Implementation Engineer STA
San Jose, California, United States
$144k-$230k/yr OnsiteFull Time
12+ YOEBachelor's in EE or Computer Engineering, 12+ years ASIC STA experience, proficiency with Cadence or Synopsys sign-off flows, SDC/constraint development, and scripting in Tcl, Python, or Perl.
Tcl, Python, Perl, Shell, Cadence, Synopsys
1w
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SR ASIC Design Verification Engineer
San Jose, California, United States
$165k-$241k/yr OnsiteFull Time
1+ YOEDegree in electrical/computer engineering or related plus multi-year ASIC verification experience; proficiency in System Verilog and UVM; ASIC verification, simulation, emulation, post-silicon debug experience; Linux and programming (C/C++, Python/Perl).
System Verilog, UVM, Veloce, Palladium, Zebu, HAPS, Linux, C/C++, Python/Perl
1mo
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Staff Engineer - ASIC Verification
San Jose, California, United States
$139k-$259k/yr HybridFull Time
8+ YOEBachelor's in CS/EE required (Master's desired), 8+ years ASIC verification experience, fluent in System Verilog, UVM, Python/Perl, knowledge of assertions, functional/code coverage and formal verification tools, strong communication.
System Verilog, UVM, Python, Perl
2mo
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ASIC Design Engineer - Pixel IP DMA
Cupertino or Sunnyvale
OnsiteFull Time
0+ YOEBachelor's degree plus 0 years experience; front-end ASIC RTL design; multimedia IP/SoC exposure; collaboration across architecture, design, verification; DMA engines and interconnects experience.
RTL design, Synthesis, AMBA (AXI/AHB/APB), Linting, Formal verification, Performance analysis
3d
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ASIC Design Engineer
San Jose, California, United States
OnsiteFull Time
BS/MS/PhD in Electrical/Computer Engineering; proficiency in RTL design using Verilog/SystemVerilog, logic and micro-architecture, familiarity with AMBA/PCIe/NAND/DDR, scripting (Python/Perl/TCL), and Linux command-line.
Verilog, SystemVerilog, AMBA, PCIe, NAND, DDR, Python, Perl, TCL, Linux
2mo
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Sr. Staff ASIC Verification Engineer
Sunnyvale or San Jose or Munich
OnsiteFull Time
15+ YOE15+ years ASIC verification experience; expert in SystemVerilog and UVM; experience with SoC/subsystem verification, ARM/RISC-V, high-speed interfaces, C/C++/SystemC; scripting with Python/Perl/Tcl/Shell; BS required, MS preferred.
SystemVerilog, UVM, C, C++, SystemC, Python, Perl, Tcl, Shell
2mo
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ASIC Verification Engineer
San Jose, California, United States
OnsiteFull Time
8+ YOE8+ years in UVM verification; RTL/gate-level verification; test plan and testbench development in C/Assembly/SystemVerilog; AMBA AXI/AHB/APB; PCIe/USB/Ethernet; scripting; repository and bug-tracking tools.
UVM, SystemVerilog, C, Assembly, Python, Shell, Perl, AMBA AXI, AHB, APB, PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART, Git, JIRA, Bitbucket, Jenkins
1mo
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ASIC Digital Design, Sr Staff Engineer
Noida or Bangalore or San Jose
OnsiteFull Time
8+ YOEBSEE/MSEE with 8+ years ASIC digital design experience; expertise in UCIe/PCIe/DDR/CXL/USB, SystemVerilog/Verilog, synthesis, CDC, formal, STA, Fusion Compiler, Perforce, and scripting (Perl/Shell).
SystemVerilog, Verilog, Fusion Compiler, Perforce, Perl, Shell
2mo
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Staff Engineer - ASIC Verification
San Jose or Folsom
$145k-$286k/yr OnsiteFull Time
6+ YOEBS in electrical engineering or computer science; 6-8 years verification; RTL debugging, scoreboarding, and code coverage; test plans and coverage definitions.
SystemVerilog, UVM, C, DDR, PCIe/NVMe, NAND
3w
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ASIC Design Engineer (Video Silicon IP) - Multimedia Lab
San Jose, California, United States
OnsiteFull Time
2+ YOEM.S./Ph.D. in EE/CE, 2+ years ASIC front-end RTL ownership, proficiency in SystemVerilog/Verilog or HLS, familiarity with UVM/DPI/C++, Python scripting, and VLSI design concepts.
SystemVerilog, Verilog, High level Synthesis (HLS), UVM, DPI, C++, Python, AXI, APB, EDA, GitHub Copilot, Claude, ChatGPT, FPGA
2mo
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SR ASIC Design Engineer - Ethernet Switch & High-Speed I/O
Santa Clara, California, United States
$175k-$300k/yr OnsiteFull Time
BS or MS in Electrical/Computer Engineering; experience with ASIC/RTL design; knowledge of Ethernet, SerDes, and high-speed I/O; scripting (Perl/Python/Shell); experience with SystemVerilog/Verilog; VCS; strong communication and problem-solving skills.
VCS, SystemVerilog, Verilog, Perl, Python, Shell, RTL design, SerDes
2mo
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Principal Engineer - Digital ASIC Design
San Jose, California, United States
$70k-$163k/yr OnsiteFull Time
10+ YOE10+ years ASIC/FPGA digital design; SystemVerilog; Cadence/Synopsys front-end; PHY/Serdes knowledge; post-silicon validation; travel up to 25%.
System Verilog, Cadence Tools, Synopsys Tools, VCS, SpyGlass, Design Compiler, PrimeTime, Lab equipment
2mo
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Senior ASIC Verification Engineer
San Jose, California, United States
RemoteFull Time
8+ YOE8+ years in networking hardware verification; UVM/SystemVerilog; RTL debugging; complex SoCs; Git/SVN; BS in CE/CS/EE.
UVM, SystemVerilog, VCS, Verdi, Git, SVN, Python, TCL, Perl, Shell, TCP/IP, RDMA, RoCE, IPSec
2mo
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AI/ML ASIC Architect
Milpitas, California, United States
$194k-$322k/yr HybridFull Time
15+ YOE15+ years hands-on ASIC/SoC/IO architecture experience; strong PCIe/UCIe/CXL, DMA know-how; ML/LLM aware; memory hierarchy optimization; ARM/x86/RISC-V host interactions.
PCIe, UCIe, CXL, DMA, NoC, HBM, GPU, TPU, xPU, NVMe
2mo
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Senior Principal Engineer, Architecture ASIC / System
Toronto or Ottawa or Burlington or Irvine or Morrisville or Santa Clara or Westborough
$192k-$255k/yr OnsiteFull Time
14+ YOESenior architect with 14+ years in system architecture for SoC; expertise in interconnects, memory hierarchies, power management, security; strong technical leadership.
IP evaluation, IP block, SoC architecture
3mo
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ASIC Technical Program Manager
San Jose, California, United States
OnsiteFull Time
5+ YOEAt least one full ASIC tape-out; RTL-to-GDSII know-how; 5+ years in technical/program management in semiconductor or hardware; external vendor interaction; strong communication; startup pace adaptability; Bachelor in Engineering/CS.
RTL, GDSII, DFT, EDA tools
1mo
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Senior Hardware Engineer (Teradyne, San Jose, CA) (San Jose, CA, US)
San Jose, California, United States
$111k-$178k/yr OnsiteFull Time
5+ YOEB.S. or M.S. in electrical engineering (or relevant field), 5+ years hardware/board design experience, high-speed digital/analog/power/FPGA/ASIC design, PCB and SI/PI experience, strong communication and mentorship skills.
DDR, PCIe, USB, SerDes, FPGA, ASIC, PCB, Signal integrity (SI), Power integrity (PI)
2d
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Hardware Engineer
Colorado Springs or Irvine or Longmont or Fremont or Rochester or San Jose
$91k-$113k/yr OnsiteFull Time
Early-career candidates pursuing or recently completing an engineering degree; familiarity with hardware, firmware, ASIC/SoC, or systems; programming and design experience through coursework or projects; strong analytical and communication skills.
Verilog/SystemVerilog, RTL, FPGA, C, C++, Assembly, Python, Java, Go, SQL, JavaScript, Git, Linux, IDE, CAD, Microsoft Office, RTOS
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