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15 rtl engineer jobs at 10 companies in Greenburgh, NY

3w
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RTL Design Engineer
New York City or Palo Alto or London
$205k-$285k/yr HybridFull Time
Normal Computing
Normal Computing: Building probabilistic AI and thermodynamic computing for semiconductor design.
Production SystemVerilog RTL experience, verification with UVM/cocotb/formal, taped-out silicon, ASIC/SoC design background, simulation and timing collaboration experience.
SystemVerilog, UVM, cocotb, formal, Chipyard, OpenTitan, CVA6, RISC-V
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1mo
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Senior FPGA Engineer
Chicago or New York City or London
$225k-$325k/yr OnsiteFull Time
DRW
DRW: Technology-driven principal trading firm operating in global financial markets
3+ YOEBachelor's in Computer or Electrical Engineering, 3+ years FPGA/hardware engineering experience, RTL/Verilog expertise, FPGA design flow experience, knowledge of TCP/IP, strong autonomous and problem-solving skills.
Verilog, System Verilog, RTL, XILINX, ALTERA, TCP/IP, synthesis, place & route, static timing analysis
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1mo
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Senior FPGA Engineer
Chicago or New York City or London or United States or Canada or Europe or Asia
OnsiteFull Time
DRW
DRW: Technology-driven principal trading firm operating in global financial markets
3+ YOEBachelor's in Computer/Electrical Engineering, 3+ years FPGA/hardware experience, Verilog/System Verilog and RTL skills, FPGA design flow (synthesis, place & route, static timing), SoC and TCP/IP knowledge, lab debugging, EM/board characterization.
Verilog, System Verilog, RTL, TCP/IP, XILINX, ALTERA
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2mo
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Distinguished Engineer, ASIC (CONTRACT)
Burlington or New York or San Francisco
HybridContract, Temporary
Butterfly Network
Butterfly NetworkNYSE: BFLY: Handheld whole-body ultrasound scanners powered by semiconductor technology.
8+ YOE8–12+ years in digital IC/ASIC/SoC design; strong RTL SystemVerilog; tapeout experience; cross-functional collaboration.
SystemVerilog, Verilog, RTL, ASIC, SoC, clock_domain, PPA tools
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3mo
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ASIC Physical Design Engineer
New York, New York, United States
$250k-$300k/yr OnsiteFull Time
Jane Street
Jane Street: Global quantitative trading firm and liquidity provider.
Experience with physical design flows (floorplanning, place-and-route, timing closure, P&R, physical verification, power analysis); able to own a flow end-to-end; read/write RTL; cross-stack thinking; programming in Python, C++, or similar.
Python, C++, RTL, OCaml, Haskell
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2mo
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Staff Engineer, Digital ASIC Design (CONTRACT)
Burlington or New York
HybridContract
Butterfly Network
Butterfly NetworkNYSE: BFLY: Handheld whole-body ultrasound scanners powered by semiconductor technology.
8+ YOEBS/MS/PhD in EE/CE; 8+ yrs in digital IC/ASIC/SoC; RTL ownership; SystemVerilog/Verilog; high-throughput datapaths; silicon constraints; SV/UVM; Python/cocotb; post-silicon bring-up.
SystemVerilog/Verilog, UVM, Python, cocotb, RTL, RTL verification, Fixed-point modeling
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4w
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Customer Projects Hardware Engineer – Aerospace, Defense & Government (ADG)
Hazlet or Portsmouth
$135k-$195k/yr OnsiteFull Time
Altera
Altera: Manufacturer of field-programmable gate arrays and programmable logic devices.
6+ YOEBachelor's in EE/CE or related, 6+ years hardware design/RTL/board-level experience, FPGA systems familiarity, high-speed interface knowledge (DDR, PCIe, Ethernet), lab debugging experience, eligible for U.S. security clearance.
oscilloscope, logic analyzer, RTL, PCIe, Ethernet, DDR
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3mo
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Design Verification (DV) Engineer
Austin or Boulder or Chicago or London or New York City
$175k-$250k/yr OnsiteFull Time
Hudson River Trading
Hudson River Trading: A quantitative firm using technology to trade global financial markets.
2+ YOE2+ years RTL verification for FPGA/ASIC; SystemVerilog/UVM; Python; Linux; Verilator; Cocotb; C++ is a plus.
SystemVerilog, UVM, Python, Verilator, Cocotb, Linux, C++
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1w
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Two Sigma Securities, Hardware Engineer
New York City, New York, United States
$165k-$300k/yr HybridFull Time
Two Sigma
Two Sigma: Systematic investment management and quantitative trading firm.
1+ YOEMinimum 1 year RTL design and verification experience, proficiency in SystemVerilog and Python, FPGA/ASIC knowledge, timing analysis, network protocol familiarity; C++ is a plus.
SystemVerilog, Python, FPGA, ASIC, C++
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FPGA Design Engineer
New York City, New York, United States
$200k-$280k/yr OnsiteFull Time
Normal Computing
Normal Computing: Building probabilistic AI and thermodynamic computing for semiconductor design.
Proven FPGA experience bringing RTL to timing-closed hardware; expert SystemVerilog/VHDL and Xilinx Vivado; PCIe and common bus protocols; strong Python/C++ for automation; board bring-up and lab debugging skills.
SystemVerilog, VHDL, Xilinx Vivado, ILA, Vivado Analyzer, Python, C++, PCIe, AXI, AHB, SPI, UART, JTAG, HAPS, VCU118, VPK180, Cocotb, UVM, OSVVM, hls4ml, FINN, GitLab CI, Docker, oscilloscope, logic analyzer
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2w
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Research Engineer, Chip Design RL (Reinforcement Learning)
San Francisco or New York City
$500k-$850k/yr HybridFull Time
Anthropic
Anthropic: Developing safe and reliable artificial intelligence systems.
Bachelor's or equivalent, expertise in ASIC/FPGA design and EDA tools, experience with RTL, verification (UVM, formal methods), physical design and tapeout experience; RL experience and tooling experience preferred.
EDA tools, UVM, formal methods, place-and-route
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1mo
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Principal Digital Design Engineer (ASIC)
Somerset or Wilmington
$160k-$239k/yr OnsiteFull Time
Analog Devices
Analog DevicesNASDAQ: ADI: Designs and manufactures semiconductors for signal processing and power management.
10+ YOE10+ years ASIC/SoC digital design experience, Bachelor’s degree in EE/CE, expertise in SystemVerilog/Verilog, RTL design, synthesis, timing closure, MATLAB/TCL/Python modeling, Cadence tools, and tapeout experience.
SystemVerilog, MATLAB, Verilog, Python, TCL, Cadence, UVM
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2mo
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Silicon Architect, Diffusion ASICs
New York City or London
$234k-$298k/yr OnsiteFull Time
Normal Computing
Normal Computing: Building probabilistic AI and thermodynamic computing for semiconductor design.
Experience in architecture/microarchitecture of high-performance digital systems; strong hardware specification and RTL collaboration; proficiency in Python or C++ for modeling; familiarity with SystemVerilog/RTL.
Python, C++, SystemVerilog, RTL, FPGA
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2w
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Senior CPU Performance Architect
Austin or Portland or Mountain View or Poughkeepsie
$163k-$237k/yr OnsiteFull Time
Google
GoogleNASDAQ: GOOGL: Provides online search, advertising, cloud computing, and consumer electronics.
8+ YOE8+ years in microprocessor architecture and performance, Bachelor's in EE/CE/CS or equivalent, RN? (ignore) BLS? (ignore) Experience with performance modeling, EM/RTL correlation, and system software knowledge.
ARM, RISC-V, x86, RTL, Linux
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1mo
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CPU Cache Subsystem Senior Design Manager
Austin or Mountain View or Portland or Poughkeepsie
$240k-$334k/yr OnsiteFull Time
Google
GoogleNASDAQ: GOOGL: Provides online search, advertising, cloud computing, and consumer electronics.
15+ YOEBachelor's in EE/CS or equivalent, 15+ years CPU design experience (load-store logic/RTL, L2/L3 caches), experience leading design teams, front-end quality check experience (Lint, CDC/RDC); ARM and mobile SoC experience preferred.
Lint, CDC/RDC, RTL, ARM instruction set architecture
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