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31 rtl engineer jobs at 10 companies in Salem, OR

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Principal PCIe CXL RTL Design Engineer
Aix-en-Provence or Sofia or Hillsboro or Bangalore
HybridFull Time
Rambus
RambusNASDAQ: RMBS: Develops high-performance memory interface chips and semiconductor IP.
5+ YOE5+ years RTL design experience; expertise in Verilog/System Verilog; Master’s degree or PhD in Electrical or Computer Engineering (or equivalent); knowledge of PCIe/CXL/AMBA; FPGA prototyping; strong English and collaboration skills.
System Verilog, Verilog, PCIe, CXL, AMBA, FPGAs
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1mo
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Sr. CPU RTL Front End Methodology Engineer
Austin or Phoenix or Hillsboro
$164k-$312k/yr OnsiteFull Time
Intel
IntelNasdaq: INTC: Designs and manufactures microprocessors and semiconductor components.
6+ YOE5+ MgmtRequires 6+ years silicon CPU logic experience, 5+ years technical leadership; degree in CS/Electrical/Electronics engineering (or related) with substantial experience; experience with RTL methodologies, front-end and back-end flows, and use of AI tools.
AI tools
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FE RTL Infrastructure - CAD Engineer
Beaverton, Oregon, United States
OnsiteFull Time
Apple
AppleNASDAQ: AAPL: Designs and sells consumer electronics, software, and online services.
Design and build infrastructure for high-performance, power-efficient processors and system-on-chip technology; collaborate within silicon and manufacturing teams.
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2mo
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Senior Engineer, Digital Design Engineering
Beaverton, Oregon, United States
$122k-$174k/yr HybridFull Time
Analog Devices
Analog DevicesNASDAQ: ADI: Designs and manufactures semiconductors for signal processing and power management.
2+ YOEMaster’s degree in Electrical/Electronic/Computer Engineering or related field; 2 years of digital design/verification experience; proficiency with RTL, Verilog/SystemVerilog, and CAD tools; knowledge of verification methods and test benches.
Verilog, SystemVerilog, Cadence, Synopsys, RTL design, Test benches, ASIC design flow
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5d
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Senior Physical Design Engineer
Hillsboro or Redmond or Mountain View or Raleigh or Austin
$120k-$235k/yr HybridFull Time
Microsoft
MicrosoftNASDAQ: MSFT: Develops software, services, devices, and cloud computing solutions.
5+ YOEExperience in SOC physical design, low-power methodology, RTL-to-GDS implementation, signoff (timing, physical verification, EMIR, formal equivalence), and collaboration across CAD, RTL, architecture, and power teams.
PrimePower
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3d
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ASIC Physical Design Engineer
Boulder or Beaverton
$149k-$277k/yr HybridFull Time
Ralliant Corporation
Ralliant CorporationNYSE: RAL: Global provider of precision instruments, sensors, and monitoring solutions.
5+ YOEBS in Electrical Engineering,5+ years ASIC/SoC physical design experience from RTL to GDS,static timing and signoff expertise,proficiency with Cadence/Synopsys/Siemens EDA and scripting (Tcl,Python,Perl,shell).
Cadence, Synopsys, Siemens EDA, Tcl, Python, Perl, shell
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3d
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ASIC Physical Design Engineer
Boulder or Beaverton or Louisville
HybridFull Time
Ralliant
RalliantNew York Stock Exchange: RAL: Sells precision instruments and sensors for diverse industrial sectors.
5+ YOEBS in Electrical Engineering, 5+ years ASIC physical design experience from RTL to GDS, proficiency with Cadence/Synopsys/Siemens EDA, static timing analysis, signoff checks, and scripting (Tcl, Python, Perl, shell).
Cadence, Synopsys, Siemens EDA, Tcl, Python, Perl, shell
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2w
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MTS Logic Design
Hillsboro, Oregon, United States
$86k-$160k/yr HybridFull Time
Rambus
RambusNASDAQ: RMBS: Designs and licenses high-performance semiconductor memory interface technologies.
Bachelor's degree in engineering, knowledge of Verilog/System Verilog, RTL design and verification, strong communication skills.
Verilog, System Verilog, RTL
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2w
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CPU Design Methodology Engineer
Hillsboro or Austin or Santa Clara or United States
$136k-$265k/yr HybridFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs GPU-accelerated computing and artificial intelligence hardware.
5+ YOEMasters in Computer/Electrical Engineering or equivalent experience,5+ years chip/SOC design experience,RTL (Verilog),UVM/System Verilog,design automation,Perl/Python skills,analytical and interpersonal skills.
Verilog, UVM, System Verilog, Perl, Python
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3w
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Senior FPGA Design Engineer (Nextest, Tualatin, OR)
Tualatin or San Jose
$170k-$273k/yr OnsiteFull Time
Teradyne
TeradyneNASDAQ: TER: Designs and manufactures automated test equipment and advanced robotics systems.
8+ YOEB.S. or M.S. in electrical engineering,8+ years relevant experience,RTL/Verilog,Intel/Xilinx tool flows,static timing analysis,FPGA transceivers,EM simulation lab validation,C/C++,Linux/Windows proficiency.
C, C++, Verilog HDL, Intel/Xilinx FPGA tool flows, UVM, Linux, Windows, oscilloscope, power supply, waveform generator, ATE
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3w
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Senior CPU Performance Architect
Austin or Portland or Mountain View or Poughkeepsie
$163k-$237k/yr OnsiteFull Time
Google
GoogleNASDAQ: GOOGL: Provides online search, advertising, cloud computing, and consumer electronics.
8+ YOE8+ years in microprocessor architecture and performance, Bachelor's in EE/CE/CS or equivalent, RN? (ignore) BLS? (ignore) Experience with performance modeling, EM/RTL correlation, and system software knowledge.
ARM, RISC-V, x86, RTL, Linux
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1mo
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Technical Director - Digital IC Design
San Jose or Hillsboro
$170k-$340k/yr OnsiteFull Time
Skyworks Solutions
Skyworks SolutionsNASDAQ: SWKS: Designs and manufactures analog and mixed-signal semiconductor solutions.
12+ YOEBachelor's in EE/CE required (Master's/PhD preferred), 12+ years in digital IC design with hardware DSP focus, proven ASIC/SoC delivery, team leadership, RTL (Verilog/SystemVerilog/SystemC), synthesis/timing/simulation, FPGA prototyping, low-power and physical design expertise.
Verilog, SystemVerilog, SystemC, JasperGold
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