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RTL Design Engineer
Irvine or United States
OnsiteFull Time
Bachelor's in Electrical Engineering; RTL design with Verilog/SystemVerilog; DSP, verification, lab bring-up; scripting knowledge; hardware-software co-design.
Verilog, SystemVerilog, Perl, Python, DSP, Formal verification
1mo
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Sr. RTL Design Engineer (Silicon Engineering)
Austin or Irvine or Redmond or Sunnyvale
$170k-$235k/yr OnsiteFull Time
5+ YOEBachelor’s in electrical/computer engineering or computer science; 5+ years of RTL implementation experience.
Verilog, SystemVerilog, Python, EDA tools, HDL simulators, HDL Lint
1mo
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Principal FPGA / RTL Design Engineer - Signal Processing
Los Angeles or Irvine
$175k-$225k/yr HybridFull Time
10+ YOEBS in ECE/CS or related; 10+ yrs RTL/FPGA design or 6+ yrs with PhD; Xilinx FPGAs, Vivado; fixed-point DSP; US person.
Xilinx FPGAs, Vivado IDE, Fixed-point arithmetic, Digital Signal Processing, MATLAB, Python, Perl
1mo
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FPGA Design Engineer
Los Angeles or Irvine
$100k-$140k/yr HybridFull Time
6+ YOESenior FPGA design expert with 6+ years (MS: 4y; PhD: 2y) in fixed-point DSP, multiple clock-domain FPGA designs, Xilinx Vivado.
Xilinx FPGA, Vivado, MATLAB, HDL, FPGA design, RTL coding
2mo
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Senior Avionics FPGA Design & Verification Engineer - TeraWave
Seattle or Los Angeles or Denver
$157k-$220k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
7+ YOE7+ years in digital design/SoC architecture; SystemVerilog/Verilog RTL; FPGA/SoC integration; timing and bus protocols; RTL simulation and debugging; hardware design verification.
SystemVerilog, Verilog, QuestaSim, FPGA, SoC, RTL, AXI, AHB
1mo
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Senior Digital Engineer
Sydney or Sydney or Irvine or Boston or Bangalore or Cambridge or Hangzhou or Taipei or Tokyo or Sydney
OnsiteFull Time
5+ YOE5+ years as Senior Digital Engineer; strong Verilog/SystemVerilog; RTL design; low-power techniques; collaborate with firmware/PHY teams.
Verilog/SystemVerilog, C, Python, Tcl, Shell, Makefiles, UPF/CPF, Scripting and automation
1mo
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Sr. FPGA Engineer
El Segundo or Los Angeles or Hawthorne
$160k-$225k/yr OnsiteFull Time
5+ YOEB.S. in engineering or CS, 5+ years FPGA/RTL experience, Verilog/SystemVerilog, Vivado toolchain, AXI protocols, ARM/SoC FPGA experience, Python/Bash scripting, U.S. Person status required.
Verilog, SystemVerilog, ARM AMBA AXI Protocol (AXI4, AXI4-Lite, AXI4-Stream), Vivado Design Suite, Zynq, Ultrascale, Ultrascale+, Versal, TCP/UDP/IP, I2C, JTAG, UART, SPI, CAN, Bash, Python, Simulink, MATLAB, C, C++, SystemC, Chisel, VHDL, git, Bitbucket CI, Jenkins, NTP, PTP, Ettus, NI, HackRF, HLS Synthesis, GPU
1mo
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Senior FPGA Engineer
Hawthorne or El Segundo or Los Angeles
$160k-$250k/yr OnsiteFull Time
8+ YOEBachelor’s in CE/EE/CS, 8+ years FPGA development with SystemVerilog or VHDL, familiarity with Xilinx Vivado/Vitis, experience with high-speed I/O and board bring-up, strong timing and RTL skills.
SystemVerilog, VHDL, Xilinx Vivado, Vitis, Xilinx Zynq Ultrascale+ MPSoC, C/C++, embedded Linux
2w
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Senior FPGA Engineer
Long Beach, California, United States
$148k-$222k/yr OnsiteFull Time
5+ YOEBachelors in EE/Computer Eng or related; 5+ years FPGA development and high-speed digital systems experience in mission-critical applications; RTL/verification/synthesis/timing expertise; cross-functional collaboration skills.
VHDL, Verilog, SystemVerilog, SpinalHDL, Chisel, Vitis, SystemC, Simulink, RISC-V, AMD Xilinx, Intel, Microchip, CI/CD
3mo
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Senior ASIC DV Engineer
San Jose or Irvine
$141k-$226k/yr OnsiteFull Time
12+ YOEBachelor’s in Engineering with 12+ years, or Master’s with 10+ years, or PhD with 7+ years; MS/PhD preferred.
UVM, AMS, Spice, RTL, Gate-level verification, ATE
3mo
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Senior Avionics Engineer
Playa Vista, California, United States
$137k-$193k/yr OnsiteFull Time
5+ YOE5+ years in design, build, and test of satellite/spacecraft flight hardware; PCB design; mixed-signal/digital design; RTL; C/C++, Python; Altium; fault-tolerant design; aerospace environment
Altium Designer, UART, I2C, SPI, RS422, RS485, CAN, PCIe, Ethernet, Oscilloscope, Multimeter, Power Supply, Spectrum Analyzer, Data Acquisition, PCB Design, Environmental Testing
3w
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Digital Design Engineer
Irvine, California, United States
$98k-$144k/yr OnsiteFull Time
1+ YOE1+ years experience designing and verifying high-performance communications/DSP ASICs; strong RTL (Verilog/System Verilog) and UNIX-based EDA tool skills; experience with verification, synthesis, lint, CDC, power analysis; MATLAB/C++ a plus.
Verilog, System Verilog, UNIX, EDA, MATLAB, C/C++
3mo
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Principal Electrical Engineer - ASIC/FPGA Mission Systems (Onsite)
El Segundo, California, United States
$118k-$225k/yr OnsiteFull Time
8+ YOE8+ years in STEM or 5+ years with advanced degree; DoD Secret clearance; RTL coding in VHDL/Verilog; ASIC/FPGA design and verification.
VHDL, Verilog, ModelSim, Synplify, Quartus, Vivado, SystemVerilog, Git, Subversion, Unix, C++, Perl
3w
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Associate ASIC/FPGA Design or Verification Engineer
El Segundo or Huntington Beach or Fairfax
$99k-$133k/yr OnsiteFull Time
2+ YOEUS citizenship with ability to obtain U.S. Secret clearance, Bachelor\u0000s degree in a relevant field, experience with ASIC/FPGA design or verification, and RTL experience with Verilog/VHDL/SystemVerilog.
Verilog, VHDL, SystemVerilog, System Verilog Assertions, UVM, Palladium, Make, Perl, Python, svn, cvs, git, Linux, ARM, JESD204C, PCIe, Ethernet
1mo
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Staff FPGA Design Engineer
Irvine, California, United States
$150k-$190k/yr OnsiteFull Time
8+ YOEBachelor's in EE/CE, 8+ years FPGA RTL architecture/development/verification, strong SystemVerilog or VHDL skills, experience with Microship Polarfire/AMD Zynq/Versal/Ultrascale, verification methodologies, Git, Python/Tcl/Bash, C/C++ on Linux, and eligibility for DoD security clearance.
SystemVerilog, VHDL, Microship Polarfire, AMD Zynq US+, Versal, AMD Ultrascale, Vivado, Mentor Modelsim/Questasim, AXI, PCIe, DDR4, DDR5, JESD204B, JESD204C, 100Gb ethernet, SPI, I2C, UART, CAN FD, LVDS, Git, Python, Tcl, Bash, Linux, C/C++
3mo
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Principal Engineer Digital Design
Irvine or California or Dallas or Texas
$164k-$241k/yr HybridFull Time
12+ YOEBachelor's degree in EE/Computer Engineering, 12+ years RTL design experience (Verilog/System Verilog), DSP algorithm implementation, fixed-point math, MATLAB/C/C++, FPGA/ASIC experience, and familiarity with EDA tools (Synopsys Design Compiler, Cadence).
Verilog, System Verilog, HDL, MATLAB, Simulink, C, C++, Synopsys Design Compiler, Cadence
1mo
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Field Application Engineer – PowerPro - Job Detail | Careers Marketplace - Siemens
Austin or Costa Mesa or Santa Clara or San Diego
$147k-$293k/yr HybridFull Time
Strong RTL design experience (Verilog/SystemVerilog/VHDL), knowledge of digital design and synthesis/verification flows, RTL power analysis experience, scripting (Tcl, Python), BS/MS in EE/CS or related field, strong communication and problem-solving skills.
PowerPro, Verilog, SystemVerilog, VHDL, Tcl, Python, PrimePower, PowerArtist, UPF, CPF, Microsoft Copilot, OpenAI APIs
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