3w
Save
Mark Applied
Hide
RTL Engineer
Mountain View, California, United States
$250k-$375k/yr OnsiteFull Time
5+ YOE5+ years RTL/SoC design to silicon, expert Verilog/SystemVerilog, synthesis/timing/CDC/SDC awareness, microarchitecture skills, collaboration across DV/PD/DFT, and scripting in Python/Tcl.
SystemVerilog, Verilog, Python, Tcl, SDC, STA, UPF, HBM, PCIe, SerDes, RISC-V, FPGA
3mo
Save
Mark Applied
Hide
RTL Design Engineer
Cupertino or United States
OnsiteFull Time
Bachelor's degree in Electrical Engineering; experience in RTL design, Verilog/SystemVerilog, DSP concepts, and circuit verification.
Verilog, SystemVerilog, linting tools, clock-domain crossing checkers, Synthesis, Static Timing Analysis, Design-for-Test, Scripting (Perl, Python), Formal verification, DSP concepts, hardware optimization
2mo
Save
Mark Applied
Hide
CPU Systems RTL Engineer
Santa Clara, California, United States
$167k-$251k/yr OnsiteFull Time
5+ YOEMS in Computer/Electrical Engineering with 5+ years CPU RTL experience; strong microarchitecture knowledge; Verilog or VHDL experience; familiarity with timing, power, and simulators; scripting with Perl or Python.
Verilog, VHDL, Perl, Python
4w
Save
Mark Applied
Hide
Senior RTL Engineer, Interconnect Design
San Francisco, California, United States
$225k-$445k/yr HybridFull Time
Senior RTL engineer with deep Verilog/SystemVerilog expertise, SoC interconnect/NoC experience, protocol knowledge (AXI, APB, CXL, PCIe, Ethernet), RTL signoff flows, and track record from microarchitecture through tape-out.
Verilog, SystemVerilog, AXI, APB, CXL, PCIe, Ethernet, RDMA, RoCE, network-on-chip, NoC, FPGA, lint, CDC/RDC, synthesis, formal verification, static timing analysis, power analysis, design-for-test
1mo
Save
Mark Applied
Hide
RTL Design Engineer
Mountain View, California, United States
$100k-$180k/yr OnsiteFull Time
8+ YOE8+ years VLSI/RTL design experience with System Verilog/Verilog, Python RTL generators, HLS, SoC integration, UPF low-power flow, synthesis/timing closure, linting and CDC/RDC checks, and emulation on Zebu/HAPS.
System Verilog, Verilog, Python, High-Level Synthesis (HLS), Zebu, HAPS, Unified Power Format (UPF)
1mo
Save
Mark Applied
Hide
RTL Design Engineer, TPU Compute
Sunnyvale, California, United States
$138k-$198k/yr OnsiteFull Time
4+ YOEBachelor's degree in EE/CE/CS or related field; 4 years digital design with SystemVerilog RTL; experience with computer architecture.
SystemVerilog, RTL, ASIC design, computer architecture, verification
1mo
Save
Mark Applied
Hide
SoC RTL Design Engineer
San Jose or Bangalore
HybridFull Time
8+ YOEBS/MS in Electrical or Computer Engineering; 8+ years in digital IC design with chip infrastructure ownership (clocking, power management, reset/DFT) at block-lead or subsystem level; strong SystemVerilog and infrastructure RTL skills; experience with embedded microcontroller integration and security features.
SystemVerilog, RTL Design, Power Management, Clock Gating, Reset, DFT, BIST, Interrupt Controller, UART, JTAG, PCIe, UCIe
2w
Save
Mark Applied
Hide
RTL Design Engineer
New York City or Palo Alto or London
$205k-$285k/yr HybridFull Time
Production SystemVerilog RTL experience, verification with UVM/cocotb/formal, taped-out silicon, ASIC/SoC design background, simulation and timing collaboration experience.
SystemVerilog, UVM, cocotb, formal, Chipyard, OpenTitan, CVA6, RISC-V
2mo
Save
Mark Applied
Hide
Sr. Engineer, RTL Implementation
Austin or Santa Clara
$100k-$500k/yr HybridFull Time
Experienced in high-performance physical design; RTL coding (Verilog/VHDL); synthesis/place-and-run; CPU micro-architecture.
Verilog, VHDL, Synthesis tools, Place and Route tools
2mo
Save
Mark Applied
Hide
Sr. RTL Design Engineer (Silicon Engineering)
Austin or Irvine or Redmond or Sunnyvale
$170k-$235k/yr OnsiteFull Time
5+ YOEBachelor’s in electrical/computer engineering or computer science; 5+ years of RTL implementation experience.
Verilog, SystemVerilog, Python, EDA tools, HDL simulators, HDL Lint
2mo
Save
Mark Applied
Hide
Senior Engineer, RTL Design
San Jose, California, United States
$138k-$206k/yr OnsiteFull Time
5+ YOEBS with 5 years RTL development or MS with 3 years; PhD in Computer/Electrical Engineering; HDL/Verilog; FPGA; PCIe/CXL/NVMe; CAD tools.
Verilog, HDL, CAD tools, Synopsys, Mentor, Cadence, FPGA, PCIe, CXL, NVMe, AXI, DDR4/5, Ethernet
3mo
Save
Mark Applied
Hide
Senior RTL Design Engineer - CPU Frontend
Santa Clara, California, United States
$159k-$194k/yr OnsiteFull Time
3+ YOE3+ years of RTL design experience; Verilog/SystemVerilog/VHDL; CPU RTL design; Chisel/Scala experience a plus; strong software engineering skills.
Verilog, SystemVerilog, VHDL, Chisel, FIRRTL, Scala, Bluespec, Git, Jira, Confluence
3mo
Save
Mark Applied
Hide
RTL Design / Microarchitecture Engineer
Sunnyvale, California, United States
$160k-$220k/yr OnsiteFull Time
5+ YOE5–10 years of RTL design and microarchitecture experience; strong SystemVerilog/Verilog expertise; ASIC/SoC development experience.
SystemVerilog, Verilog, Synopsys VCS, Cadence Xcelium, Synopsys Design Compiler, Scripting (Python/TCL)
2mo
Save
Mark Applied
Hide
Lead RTL Design Engineer
Austin or Pittsburgh or San Jose
$160k-$250k/yr OnsiteFull Time
8+ YOE8+ years RTL design with tape-out ownership; SystemVerilog; on-chip networks, memory subsystems, NoC; low-power design; DV collaboration; silicon bring-up.
SystemVerilog, UPF, AXI, AHB, APB, TileLink, NoC, SDC, STA, ATPG, DFT, memory compiler
1d
Save
Mark Applied
Hide
Digital Design RTL Engineer
Fort Collins or San Jose
$122k-$195k/yr OnsiteFull Time
8+ YOEBSEE required; 8+ years experience in SoC integration with RTL design in advanced nodes, SystemVerilog proficiency, PPA/CDC/RDC and low-power design knowledge; EMR not mentioned.
SystemVerilog
1mo
Save
Mark Applied
Hide
Senior Engineer, GPU RTL Design
Austin or San Jose
$124k-$208k/yr OnsiteFull Time
4+ YOEMaster’s in Electrical/Computer Engineering required for senior/staff; Senior requires 4+ years. Requires RTL design experience (Verilog/SystemVerilog), ASIC front-end flow familiarity, microarchitecture knowledge, and ability to access export-controlled information.
Verilog, SystemVerilog
2d
Save
Mark Applied
Hide
RTL Power Optimization Engineer – New College Grad 2026
Santa Clara, California, United States
$116k-$219k/yr OnsiteFull Time
MS or PhD in EE/CE (pursuing or recent); understanding of RTL low-power design, backend flows, power analysis tools; Python and ML experience; strong communication and RTL debugging skills.
PowerArtist, PrimeTime PX, Python, Verilog
2mo
Save
Mark Applied
Hide
Member of Technical Staff, Hardware, RTL Design Engineer
Palo Alto or Austin
$200k-$420k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE and 5+ years industry experience with advanced process nodes (7nm or below); strong RTL, synthesis, physical design, and timing tool experience; expertise in computer architecture and silicon delivery.
System Verilog, VCS, Verdi, Fusion Compiler, PrimeTime, C, C++, python, ISA assembly, PCIe, UCIe, HBM, DDR, AXI, CHI, Static Timing Analysis (STA)
2d
Save
Mark Applied
Hide
RTL Power Optimization Engineer – New College Grad 2026
Santa Clara, California, United States
$116k-$219k/yr OnsiteFull Time
MS or PhD in EE/CE or equivalent; understanding of RTL power optimization, low-power techniques, backend flows, experience with power analysis tools, and strong Python and communication skills.
PowerArtist, PrimeTime PX, Python, Verilog
6d
Save
Mark Applied
Hide
Senior Memory Controller RTL Design Engineer
Redmond or Mountain View or Raleigh or Austin or Hillsboro
$120k-$235k/yr HybridFull Time
1+ YOEDegree in EE/CE/CS or equivalent with 1–5+ years experience depending on degree, strong Verilog/SystemVerilog RTL design skills, DDR4/DDR5 controller experience preferred, scripting (Perl/Tcl/Python), familiarity with front-end verification and low-power/timing checks, ability to pass Microsoft security and export control screenings.
Verilog, System Verilog, Perl, Tcl, Python
Explore Jobs
Expand Your Job Search
Top Cities Near Richmond for Rtl Engineer
- Rtl Engineer jobs in San Jose, CA
- Rtl Engineer jobs in San Francisco, CA
- Rtl Engineer jobs in Oakland, CA
- Rtl Engineer jobs in Fremont, CA
- Rtl Engineer jobs in Santa Rosa, CA
- Rtl Engineer jobs in Hayward, CA
- Rtl Engineer jobs in Sunnyvale, CA
- Rtl Engineer jobs in Concord, CA
- Rtl Engineer jobs in Santa Clara, CA
- Rtl Engineer jobs in Vallejo, CA
- Rtl Engineer jobs in Berkeley, CA
- Rtl Engineer jobs in Fairfield, CA
- Rtl Engineer jobs in Antioch, CA
- Rtl Engineer jobs in Daly City, CA
- Rtl Engineer jobs in San Mateo, CA
- Rtl Engineer jobs in Vacaville, CA
- Rtl Engineer jobs in San Leandro, CA
- Rtl Engineer jobs in Livermore, CA
- Rtl Engineer jobs in Redwood City, CA
- Rtl Engineer jobs in Mountain View, CA