3w
Save
Mark Applied
Hide
Senior RTL Engineer, Interconnect Design
San Francisco, California, United States
$225k-$445k/yr HybridFull Time
Senior RTL engineer with deep Verilog/SystemVerilog expertise, SoC interconnect/NoC experience, protocol knowledge (AXI, APB, CXL, PCIe, Ethernet), RTL signoff flows, and track record from microarchitecture through tape-out.
Verilog, SystemVerilog, AXI, APB, CXL, PCIe, Ethernet, RDMA, RoCE, network-on-chip, NoC, FPGA, lint, CDC/RDC, synthesis, formal verification, static timing analysis, power analysis, design-for-test
2mo
Save
Mark Applied
Hide
PHY RTL Design Engineer
Los Angeles or San Diego or San Francisco
OnsiteFull Time
Bachelor's in related field; DSP fundamentals; digital communications; RTL design experience; strong communication skills.
MATLAB, RTL Design, UVM, DV, FPGA, Emulation, Synthesis, Power Analysis, EDA Tools
2w
Save
Mark Applied
Hide
RTL Design Engineer
New York City or Palo Alto or London
$205k-$285k/yr HybridFull Time
Production SystemVerilog RTL experience, verification with UVM/cocotb/formal, taped-out silicon, ASIC/SoC design background, simulation and timing collaboration experience.
SystemVerilog, UVM, cocotb, formal, Chipyard, OpenTitan, CVA6, RISC-V
2mo
Save
Mark Applied
Hide
Member of Technical Staff, Hardware, RTL Design Engineer
Palo Alto or Austin
$200k-$420k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE and 5+ years industry experience with advanced process nodes (7nm or below); strong RTL, synthesis, physical design, and timing tool experience; expertise in computer architecture and silicon delivery.
System Verilog, VCS, Verdi, Fusion Compiler, PrimeTime, C, C++, python, ISA assembly, PCIe, UCIe, HBM, DDR, AXI, CHI, Static Timing Analysis (STA)
3mo
Save
Mark Applied
Hide
Principal Digital Design Engineer
Chandler or Vancouver or Remote
$200k-$250k/yr HybridFull Time
10+ YOEBachelor's or master's in electrical/computer engineering; 10+ years in digital design with RTL; SoC/subsystem tapeout experience; strong RTL, microarchitecture, back-end flows, DFT/scan, LEC, STA, SDC skills; solid timing, power, and debug expertise.
Synopsys, Cadence, EDA tools, Synthesis, DFT, LEC, STA, SDC, UPF/CPF, RTL
3mo
Save
Mark Applied
Hide
Sr. Engineer, Performance Infrastructure
Austin or San Francisco
HybridFull Time
Proficient in C++ and Python; experience with CPU performance analysis, verification, and RTL debugging; familiarity with pre-silicon and post-silicon workflows; strong problem-solving and automation skills.
C++, Python, RTL, simulation, emulation, compilation tools
1mo
Save
Mark Applied
Hide
Senior FPGA Engineer - Control Systems
Boulder or Austin or Berkeley
$140k-$175k/yr OnsiteFull Time
Atom Computing: Building scalable quantum computers using arrays of neutral atoms.
5+ YOESenior FPGA engineer with 5+ years in FPGA/digital design; BS in EE/Physics or related field; strong SystemVerilog, RTL, Xilinx Vivado, Zynq, C/C++, Python; Linux experience; willing to learn quantum concepts.
RTL, SystemVerilog, VHDL, Vivado, Xilinx Zynq, Git, Yocto, C, C++, Python, Linux, Prototyping
3w
Save
Mark Applied
Hide
AI Silicon, Digital Design Engineer
Palo Alto, California, United States
OnsiteFull Time
8+ YOEB.S. or M.S. in EE/Computer Engineering, 8+ years ASIC/SoC digital design experience, Verilog RTL expertise, EDA tool proficiency, synthesis/timing/LEC experience, and mentorship/communication skills.
Verilog, RTL, EDA tools, Logical Equivalence Checking (LEC), Clock Domain Crossing (CDC), Reset Domain Crossing (RDC)
1mo
Save
Mark Applied
Hide
Distinguished Engineer, ASIC (CONTRACT)
Burlington or New York or San Francisco
HybridContract, Temporary
8+ YOE8–12+ years in digital IC/ASIC/SoC design; strong RTL SystemVerilog; tapeout experience; cross-functional collaboration.
SystemVerilog, Verilog, RTL, ASIC, SoC, clock_domain, PPA tools
3mo
Save
Mark Applied
Hide
FPGA Verification Engineer - Avionics
Saratoga, California, United States
$150k-$250k/yr OnsiteFull Time
4+ YOE4+ years FPGA/ASIC verification; SystemVerilog/UVM; develop verification environments; RTL simulation; functional coverage; timing analysis.
SystemVerilog, UVM, RTL simulators, VCS, QuestaSim, Python, TCL, lint, CDC analysis tools
3mo
Save
Mark Applied
Hide
Member of Technical Staff - Microarchitect / RTL Design
Palo Alto or Bangalore
OnsiteFull Time
5+ YOE5+ years RTL design; ASIC/SoC experience; SystemVerilog; AXI/AMBA interfaces; Python tooling; leadership potential.
SystemVerilog, AXI, AMBA, Python, Xilinx Vivado
3w
Save
Mark Applied
Hide
Staff Silicon Validation Engineer
Palo Alto, California, United States
$186k-$232k/yr OnsiteFull Time
Bachelor's degree in EE/CSE or related, proficiency in C/C++, Python and Linux shell, experience with SoC/FPGA validation preferred (AMD Petalinux, RTL), strong analytical and communication skills.
C, C++, Python, Linux shell, AMD Petalinux, FPGA, RTL
1w
Save
Mark Applied
Hide
Hardware Engineer - FPGA
Milpitas or San Francisco
$152k-$222k/yr OnsiteFull Time
7+ YOEExperienced FPGA/ASIC engineer with RTL (Verilog/SystemVerilog) skills, FPGA tool experience, 7+ years (BS) or 4+ years (MS), verification experience (UVM/VMM) preferred.
Verilog, SystemVerilog, UVM, VMM
1mo
Save
Mark Applied
Hide
FPGA Engineer
El Segundo or Los Angeles or Washington or San Francisco or Seattle or London
$160k-$225k/yr OnsiteFull Time
5+ YOEBachelor's in a relevant field, 5+ years FPGA RTL design experience, Verilog/SystemVerilog, AXI protocols, Vivado and SoC FPGA experience, Bash/Python scripting, U.S. Person required.
Verilog, SystemVerilog, AXI4, AXI4-Lite, AXI4-Stream, Vivado Design Suite, Zynq, Ultrascale, Ultrascale+, Versal, TCP, UDP, IP, I2C, JTAG, UART, SPI, CAN, Bash, Python, Simulink, MATLAB, C, C++, SystemC, Chisel, VHDL, git, Bitbucket CI, Jenkins
4d
Save
Mark Applied
Hide
Design Verification Engineer (Silicon Engineering)
Palo Alto, California, United States
$135k-$210k/yr OnsiteFull Time
1+ YOEBachelor's in EE/CS/CompE,1+ years design verification experience, SystemVerilog/UVM, Python/MATLAB scripting, testbench and coverage development, RTL and pre/post-silicon validation experience.
SystemVerilog, UVM, Python, MATLAB
1mo
Save
Mark Applied
Hide
Staff Electrical Engineer – FPGA / MPSoC Systems & Digital Signal Processing
San Leandro, California, United States
$160k-$240k/yr OnsiteFull Time
5+ YOE5+ years in FPGA/MPSoC design, DSP for real-time systems, MATLAB/Python, HDL/RTL, and hardware-software integration.
HDL/RTL, MATLAB, Python, FPGA, MPSoC, Digital Signal Processing, Schematic reading, Oscilloscopes, Logic Analyzers
5d
Save
Mark Applied
Hide
Research Engineer, Chip Design RL (Reinforcement Learning)
San Francisco or New York City
$500k-$850k/yr HybridFull Time
Bachelor's or equivalent, expertise in ASIC/FPGA design and EDA tools, experience with RTL, verification (UVM, formal methods), physical design and tapeout experience; RL experience and tooling experience preferred.
EDA tools, UVM, formal methods, place-and-route
2mo
Save
Mark Applied
Hide
Lead ASIC/FPGA Design Engineer
Livermore, California, United States
OnsiteFull Time
5+ YOELead RTL design of high-speed ASIC/FPGA modem; strong DSP, FEC integration, and power/performance optimizations; requires security clearance.
Verilog, SystemVerilog, LINT, CDC, RDC, Test benche s, Synthesis, Power/Area analysis, STA, Place and Route
1mo
Save
Mark Applied
Hide
Senior Engineer Space Electronics
Pleasanton, California, United States
$142k-$186k/yr OnsiteFull Time
3+ YOEBachelor's in EE (or related) with 6+ yrs or Master's with 3+ yrs; 3+ yrs space/LEO electronics design; experience with power, analog, mixed‑signal, radiation testing/mitigation; LTSpice proficiency; high‑speed PCB design and lab test equipment experience; must be U.S. Person.
LTSpice, FPGA, MCU, RTL, AS9100, Oscilloscope, VNA, Spectrum Analyzer, Power Supply, Function Generator, DVM
2mo
Save
Mark Applied
Hide
PD - Sr Staff — CAD & Design Methodology | RTL-to-GDSII Flow | Advanced Node Methodology |
Bay Area, California, United States
OnsiteFull Time
15+ YOE15+ years ASIC CAD, design methodology, and physical design; multi-node, multi-foundry platform deployments; R2G across major nodes; UPF/CPF flows; clocking and chiplet/2.5D methods.
EDA tools, RTL-to-GDSII
Explore Jobs
Expand Your Job Search
Top Cities Near Vallejo for Rtl Engineer
- Rtl Engineer jobs in San Francisco, CA
- Rtl Engineer jobs in Oakland, CA
- Rtl Engineer jobs in Fremont, CA
- Rtl Engineer jobs in Santa Rosa, CA
- Rtl Engineer jobs in Hayward, CA
- Rtl Engineer jobs in Concord, CA
- Rtl Engineer jobs in Berkeley, CA
- Rtl Engineer jobs in Fairfield, CA
- Rtl Engineer jobs in Antioch, CA
- Rtl Engineer jobs in Richmond, CA
- Rtl Engineer jobs in Daly City, CA
- Rtl Engineer jobs in San Mateo, CA
- Rtl Engineer jobs in Vacaville, CA
- Rtl Engineer jobs in San Leandro, CA
- Rtl Engineer jobs in Livermore, CA
- Rtl Engineer jobs in Redwood City, CA
- Rtl Engineer jobs in Napa, CA
- Rtl Engineer jobs in Pleasanton, CA
- Rtl Engineer jobs in Alameda, CA
- Rtl Engineer jobs in San Ramon, CA