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RTL Design Engineer
San Jose, California, United States
HybridFull Time
Experience in RTL digital design and verification, Verilog/System Verilog, scripting (Perl/Tcl/Python), FPGA/SoC design concepts, and strong analytical and communication skills; Bachelor’s or Master’s in Computer or Electrical Engineering.
Verilog, System Verilog, Perl, Tcl, Python
1mo
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Senior Field Security Applications Engineer
Campbell or Austin or United States
$140k-$190k/yr FieldFull Time
5+ YOE5+ years SoC design and verification experience with Verilog/VHDL/SystemVerilog, RTL simulation/emulation tools, strong presentation skills, willingness to travel, US citizenship required.
Verilog, VHDL, SystemVerilog, RTL Simulation, Emulation, Synopsys, Cadence, Siemens, Cycuity Radix, Cycuity HW, FPGA-based Prototyping
2mo
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FPGA / VLSI Engineer
Saratoga, California, United States
$120k-$220k/yr OnsiteFull Time
Design and verify RTL/FPGA, perform FPGA prototyping, and system integration for ASIC/SoC platforms; strong SystemVerilog/Verilog; experience with UVM; VHDL is a plus.
SystemVerilog, Verilog, UVM, VHDL, FPGA, SoC
3mo
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Sr. Staff HW Engineer – ASIC Implementation
Los Gatos or Cleveland
OnsiteFull Time
10+ YOE10+ years ASIC digital implementation experience; RTL-to-synthesis, timing closure, UPF, tapeout readiness, and script-driven automation.
Design Compiler, Fusion Compiler, PrimeTime, UPF, PrimePower, Python, Tcl
2mo
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Senior CAD Manager — RTL-to-GDS Methodology & Infrastructure, Annapurna Labs
Cupertino, California, United States
$240k-$324k/yr OnsiteFull Time
15+ YOE5+ MgmtBachelor's in electrical or computer engineering; 15+ years in semiconductor CAD/EDA or physical design; 5+ years in leadership; experience with RTL-to-GDS toolchains; knowledge of low-power design and automation.
Tcl, Python, Perl, Git, Perforce, LSF, Slurm
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