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Staff Engineer - ASIC Verification
San Jose, California, United States
$139k-$259k/yr HybridFull Time
8+ YOEBachelor's in CS/EE required (Master's desired), 8+ years ASIC verification experience, fluent in System Verilog, UVM, Python/Perl, knowledge of assertions, functional/code coverage and formal verification tools, strong communication.
System Verilog, UVM, Python, Perl
3mo
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ASIC/SoC Design Engineer
San Jose or United States
$146k-$250k/yr OnsiteFull Time
Experience in ASIC/SoC design, RTL/verification, Verilog/SystemVerilog, timing constraints, PD integration, DFT, and cross-domain collaboration.
Verilog, SystemVerilog, SystemVerilog Assertions, SDC timing constraints, ASIC CAD tools, AMBA AXI/AXI-S/APB, UPF, Perl, Python, Makefile
2mo
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Senior ASIC Design Engineer – Processor Subsystem
Saratoga, California, United States
$150k-$220k/yr OnsiteFull Time
7+ YOESenior ASIC/SoC design with processor subsystem integration and RTL expertise.
SystemVerilog, VHDL, AMBA (AHB, APB, AXI), Synopsys VCS, Cadence Xcelium, Mentor Questa
1mo
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ASIC Design Engineer, Cloud-Scale Machine Learning Acceleration team - Annapurna Labs
Cupertino or Austin
$157k-$213k/yr OnsiteFull Time
Bachelor's in Electrical Engineering (required), experience debugging and verifying designs from IP to SoC, proficiency in SystemVerilog, strong analytical and problem-solving skills.
SystemVerilog, Python, Perl
3mo
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Sr. Staff HW Engineer – ASIC Implementation
Los Gatos or Cleveland
OnsiteFull Time
10+ YOE10+ years ASIC digital implementation experience; RTL-to-synthesis, timing closure, UPF, tapeout readiness, and script-driven automation.
Design Compiler, Fusion Compiler, PrimeTime, UPF, PrimePower, Python, Tcl
3mo
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Staff - Principal, Software Engineer, SDK
Saratoga, California, United States
$210k-$275k/yr OnsiteFull Time
10+ YOEBachelor’s in CS/ECE with 10+ years (or MS with 5+), strong Ethernet L2/L3, C/C++/Python, SDK development for Ethernet switch silicon, NOS like SONiC, and ASIC/SoC experience.
C/C++, Python, Linux, SONiC, BMv2, RTL simulations
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