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RTL Design Engineer
Irvine or United States
OnsiteFull Time
Bachelor's in Electrical Engineering; RTL design with Verilog/SystemVerilog; DSP, verification, lab bring-up; scripting knowledge; hardware-software co-design.
Verilog, SystemVerilog, Perl, Python, DSP, Formal verification
1mo
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Sr. RTL Design Engineer (Silicon Engineering)
Austin or Irvine or Redmond or Sunnyvale
$170k-$235k/yr OnsiteFull Time
5+ YOEBachelor’s in electrical/computer engineering or computer science; 5+ years of RTL implementation experience.
Verilog, SystemVerilog, Python, EDA tools, HDL simulators, HDL Lint
1mo
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Principal FPGA / RTL Design Engineer - Signal Processing
Los Angeles or Irvine
$175k-$225k/yr HybridFull Time
10+ YOEBS in ECE/CS or related; 10+ yrs RTL/FPGA design or 6+ yrs with PhD; Xilinx FPGAs, Vivado; fixed-point DSP; US person.
Xilinx FPGAs, Vivado IDE, Fixed-point arithmetic, Digital Signal Processing, MATLAB, Python, Perl
1mo
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FPGA Design Engineer
Los Angeles or Irvine
$100k-$140k/yr HybridFull Time
6+ YOESenior FPGA design expert with 6+ years (MS: 4y; PhD: 2y) in fixed-point DSP, multiple clock-domain FPGA designs, Xilinx Vivado.
Xilinx FPGA, Vivado, MATLAB, HDL, FPGA design, RTL coding
2mo
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Programmable Logic Design Engineer
Germantown or Carlsbad or Independence or Englewood
$156k-$246k/yr OnsiteContract
5+ YOEBachelor's degree in Electrical/Computer Engineering; 5-8 years FPGA design; SystemVerilog; RTL design for signal processing; FPGA modules; strong communication; distribution teamwork.
System Verilog, Verilog, VHDL, Xilinx Vivado, RTL design, FPGA design, Testbench development, Simulation
2mo
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Senior Digital Engineer
Sydney or Sydney or Irvine or Boston or Bangalore or Cambridge or Hangzhou or Taipei or Tokyo or Sydney
OnsiteFull Time
5+ YOE5+ years as Senior Digital Engineer; strong Verilog/SystemVerilog; RTL design; low-power techniques; collaborate with firmware/PHY teams.
Verilog/SystemVerilog, C, Python, Tcl, Shell, Makefiles, UPF/CPF, Scripting and automation
3mo
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Senior ASIC DV Engineer
San Jose or Irvine
$141k-$226k/yr OnsiteFull Time
12+ YOEBachelor’s in Engineering with 12+ years, or Master’s with 10+ years, or PhD with 7+ years; MS/PhD preferred.
UVM, AMS, Spice, RTL, Gate-level verification, ATE
2mo
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Staff Digital Design Engineer
San Diego, California, United States
$139k-$232k/yr OnsiteFull Time
6+ YOEDesign digital subsystems for phased array and communication systems; RTL/SystemVerilog; SoC integration; embedded software in C; timing analysis; ECOs; SPI/QSPI and high-speed serial interfaces; Bachelor's or Master's in Electrical Engineering; 6+ years digital ASIC/SoC design.
SystemVerilog, Verilog, C, SPI, QSPI, JESD204B/C, Synthesis, Place-and-Route, UVM, ECOs, RISC-V, embedded software
3w
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Digital Design Engineer
Irvine, California, United States
$98k-$144k/yr OnsiteFull Time
1+ YOE1+ years experience designing and verifying high-performance communications/DSP ASICs; strong RTL (Verilog/System Verilog) and UNIX-based EDA tool skills; experience with verification, synthesis, lint, CDC, power analysis; MATLAB/C++ a plus.
Verilog, System Verilog, UNIX, EDA, MATLAB, C/C++
1mo
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Staff FPGA Design Engineer
Irvine, California, United States
$150k-$190k/yr OnsiteFull Time
8+ YOEBachelor's in EE/CE, 8+ years FPGA RTL architecture/development/verification, strong SystemVerilog or VHDL skills, experience with Microship Polarfire/AMD Zynq/Versal/Ultrascale, verification methodologies, Git, Python/Tcl/Bash, C/C++ on Linux, and eligibility for DoD security clearance.
SystemVerilog, VHDL, Microship Polarfire, AMD Zynq US+, Versal, AMD Ultrascale, Vivado, Mentor Modelsim/Questasim, AXI, PCIe, DDR4, DDR5, JESD204B, JESD204C, 100Gb ethernet, SPI, I2C, UART, CAN FD, LVDS, Git, Python, Tcl, Bash, Linux, C/C++
2mo
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Principal DFT Engineer
Carlsbad, California, United States
$155k-$193k/yr OnsiteFull Time
9+ YOELead DFT on SOC; design/verify DFT; optimize test yield and cost; mentor team.
Verilog, VHDL, RTL, ATPG, MBIST, JTAG, DC/AC analysis, Synthesis, Simulation, ATE
3mo
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Principal Engineer Digital Design
Irvine or California or Dallas or Texas
$164k-$241k/yr HybridFull Time
12+ YOEBachelor's degree in EE/Computer Engineering, 12+ years RTL design experience (Verilog/System Verilog), DSP algorithm implementation, fixed-point math, MATLAB/C/C++, FPGA/ASIC experience, and familiarity with EDA tools (Synopsys Design Compiler, Cadence).
Verilog, System Verilog, HDL, MATLAB, Simulink, C, C++, Synopsys Design Compiler, Cadence
1mo
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Field Application Engineer – PowerPro - Job Detail | Careers Marketplace - Siemens
Austin or Costa Mesa or Santa Clara or San Diego
$147k-$293k/yr HybridFull Time
Strong RTL design experience (Verilog/SystemVerilog/VHDL), knowledge of digital design and synthesis/verification flows, RTL power analysis experience, scripting (Tcl, Python), BS/MS in EE/CS or related field, strong communication and problem-solving skills.
PowerPro, Verilog, SystemVerilog, VHDL, Tcl, Python, PrimePower, PowerArtist, UPF, CPF, Microsoft Copilot, OpenAI APIs
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