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321 rtl engineer jobs at 70 companies in Watsonville, CA

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RTL Engineer
Mountain View, California, United States
$250k-$375k/yr OnsiteFull Time
DensityAI
DensityAI: Designing custom AI hardware accelerators for large language models.
5+ YOE5+ years RTL/SoC design to silicon, expert Verilog/SystemVerilog, synthesis/timing/CDC/SDC awareness, microarchitecture skills, collaboration across DV/PD/DFT, and scripting in Python/Tcl.
SystemVerilog, Verilog, Python, Tcl, SDC, STA, UPF, HBM, PCIe, SerDes, RISC-V, FPGA
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RTL integration Engineer
San Jose, California, United States
$144k-$230k/yr OnsiteFull Time
Broadcom
BroadcomNASDAQ: AVGO: Designs and sells semiconductors and infrastructure software to enterprises.
12+ YOEBachelor's plus 12+ years experience; deep RTL, UVM/SystemVerilog, synthesis, timing, CDC/RDC, GLS, SDF simulations, NCSim/VCS, Palladium modeling, STA, and strong debugging and communication skills.
RTL, UVM, SystemVerilog, SDF, NCSim, VCS, Palladium
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3w
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RTL Design Engineer
San Jose, California, United States
HybridFull Time
AMD
AMDNASDAQ: AMD: Designs and manufactures computer processors and graphics technology.
Experience in RTL digital design and verification, Verilog/System Verilog, scripting (Perl/Tcl/Python), FPGA/SoC design concepts, and strong analytical and communication skills; Bachelor’s or Master’s in Computer or Electrical Engineering.
Verilog, System Verilog, Perl, Tcl, Python
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2mo
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SoC RTL Design Engineer
San Jose or Bangalore
HybridFull Time
TylSemi
TylSemi: Building chiplet-native infrastructure for high-performance AI systems.
8+ YOEBS/MS in Electrical or Computer Engineering; 8+ years in digital IC design with chip infrastructure ownership (clocking, power management, reset/DFT) at block-lead or subsystem level; strong SystemVerilog and infrastructure RTL skills; experience with embedded microcontroller integration and security features.
SystemVerilog, RTL Design, Power Management, Clock Gating, Reset, DFT, BIST, Interrupt Controller, UART, JTAG, PCIe, UCIe
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4w
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RTL Design Engineer
New York City or Palo Alto or London
$205k-$285k/yr HybridFull Time
Normal Computing
Normal Computing: Building probabilistic AI and thermodynamic computing for semiconductor design.
Production SystemVerilog RTL experience, verification with UVM/cocotb/formal, taped-out silicon, ASIC/SoC design background, simulation and timing collaboration experience.
SystemVerilog, UVM, cocotb, formal, Chipyard, OpenTitan, CVA6, RISC-V
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TPU RTL Design Engineer
Sunnyvale, California, United States
$138k-$198k/yr OnsiteFull Time
Google
GoogleNASDAQ: GOOGL: Provides online search, advertising, cloud computing, and consumer electronics.
2+ YOEBachelor's degree or equivalent,2+ years ASIC RTL design experience focused on clocking/reset/timing-critical RTL,SystemVerilog and scripting (Python/Tcl/Perl) proficiency,experience with clock control and verification.
SystemVerilog, Python, Tcl, Perl
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FE RTL Infrastructure - CAD Engineer
Cupertino, California, United States
OnsiteFull Time
Apple
AppleNASDAQ: AAPL: Designs and sells consumer electronics, software, and online services.
Design and build infrastructure for RTL/CAD to support next-generation high-performance, power-efficient processors and SoCs.
RTL, CAD, SoC
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2mo
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Sr. Engineer, RTL Implementation
Austin or Santa Clara
$100k-$500k/yr HybridFull Time
Tenstorrent
Tenstorrent: Designs and manufactures AI processors and RISC-V CPU solutions.
Experienced in high-performance physical design; RTL coding (Verilog/VHDL); synthesis/place-and-run; CPU micro-architecture.
Verilog, VHDL, Synthesis tools, Place and Route tools
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Sr. RTL Design Engineer (Silicon Engineering)
Austin or Irvine or Redmond or Sunnyvale
$170k-$235k/yr OnsiteFull Time
SpaceX
SpaceX: Designs and launches advanced rockets and satellite internet constellations.
5+ YOEBachelor’s in electrical/computer engineering or computer science; 5+ years of RTL implementation experience.
Verilog, SystemVerilog, Python, EDA tools, HDL simulators, HDL Lint
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Senior Engineer, RTL Design
San Jose, California, United States
$138k-$206k/yr OnsiteFull Time
Samsung Semiconductor
Samsung SemiconductorKorea Exchange: 005930: Designs and manufactures memory chips, processors, and sensors.
5+ YOEBS with 5 years RTL development or MS with 3 years; PhD in Computer/Electrical Engineering; HDL/Verilog; FPGA; PCIe/CXL/NVMe; CAD tools.
Verilog, HDL, CAD tools, Synopsys, Mentor, Cadence, FPGA, PCIe, CXL, NVMe, AXI, DDR4/5, Ethernet
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1mo
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Senior Engineer, GPU RTL Design
Austin or San Jose
$124k-$208k/yr OnsiteFull Time
Samsung Electronics
Samsung ElectronicsKorea Exchange: 005930: Develops and manufactures consumer electronics, semiconductors, and mobile devices.
4+ YOEMaster’s in Electrical/Computer Engineering required for senior/staff; Senior requires 4+ years. Requires RTL design experience (Verilog/SystemVerilog), ASIC front-end flow familiarity, microarchitecture knowledge, and ability to access export-controlled information.
Verilog, SystemVerilog
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Staff RTL Design Engineer - CPU LS/PF/MMU
Santa Clara or Austin
$179k-$219k/yr OnsiteFull Time
SiFive
SiFive: Designs and licenses high-performance RISC-V processor intellectual property.
3+ YOEBS/MS in CS/CE/EE or equivalent, 3+ years design experience, CPU RTL design experience, proficiency in Verilog/System Verilog/VHDL, strong software engineering (OOP, functional, TDD), verification skills (SVA, coverage).
Chisel, FIRRTL, Verilog, System Verilog, VHDL, Scala, Bluespec, RISC-V, Git/Github, Jira, Confluence, SVA
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1w
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RTL Power Optimization Engineer – New College Grad 2026
Santa Clara, California, United States
$116k-$219k/yr OnsiteFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs GPU-accelerated computing and artificial intelligence hardware.
MS or PhD in EE/CE (pursuing or recent); understanding of RTL low-power design, backend flows, power analysis tools; Python and ML experience; strong communication and RTL debugging skills.
PowerArtist, PrimeTime PX, Python, Verilog
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2mo
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Member of Technical Staff, Hardware, RTL Design Engineer
Palo Alto or Austin
$200k-$420k/yr OnsiteFull Time
River AI
River AI: Building user-controlled, personalized AI with integrated local hardware.
5+ YOEBachelor's in EE/CE and 5+ years industry experience with advanced process nodes (7nm or below); strong RTL, synthesis, physical design, and timing tool experience; expertise in computer architecture and silicon delivery.
System Verilog, VCS, Verdi, Fusion Compiler, PrimeTime, C, C++, python, ISA assembly, PCIe, UCIe, HBM, DDR, AXI, CHI, Static Timing Analysis (STA)
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RTL Design and Architect lead
San Jose or Austin
OnsiteFull Time
Quest Global
Quest Global: Global engineering services for product development and lifecycle management.
10+ YOE10+ years industry experience, Bachelor's/Master's in Electronics/Electrical Engineering, SOC project leadership, RTL design with VHDL/Verilog/SystemVerilog, strong digital design fundamentals, exposure to micro-processor integration and high-speed peripherals, Python familiarity.
VHDL, Verilog, SystemVerilog, Python, GDSII, DDR, PCIe, UCIe, Ethernet
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2mo
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Senior Principal Engineer, Micro-architecture and RTL
Santa Clara, California, United States
$182k-$273k/yr OnsiteFull Time
Marvell
MarvellNASDAQ: MRVL: Designs and develops high-performance semiconductor and infrastructure solutions.
15+ YOEBachelor's in CS/EE with 15+ yrs; MS with 10-12 yrs; PhD with 8-10 yrs. SystemVerilog RTL, UVM, Ethernet, PCIe, CXL experience; leadership ability.
SystemVerilog, SystemVerilog Assertions, Universal Verification Methodology, RTL, PCIe, CXL, Ethernet
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Micro-Architect and RTL Designer
Mountain View, California, United States
$120k-$600k/yr HybridFull Time
MatX
MatX: Developing custom silicon chips optimized for large language models.
4+ YOEConcept-to-silicon ASIC/SoC experience; 4+ years with SystemVerilog, Python, C/C++; production micro-architecture and RTL design experience; synthesis, timing closure, verification collaboration, and high-performance compute or high-speed I/O experience.
SystemVerilog, Python, C/C++
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Digital IC Design Engineer | BCP
Santa Clara, California, United States
$130k-$241k/yr OnsiteFull Time
Texas Instruments
Texas InstrumentsNASDAQ: TXN: Designs and manufactures semiconductors and integrated circuits.
3+ YOEB.S. in Electrical Engineering, 3+ years digital design experience; RTL/Verilog/SystemVerilog, Cadence, Python, UVM, and GDSII experience preferred; ability to implement and verify synthesizable RTL to GDSII.
RTL, Verilog/Systemverilog, Cadence, Python, UVM, VAMS, GDSII
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2mo
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Staff Design Engineer
San Jose, California, United States
$145k-$246k/yr OnsiteFull Time
Micron Technology
Micron TechnologyNASDAQ: MU: Designs and manufactures semiconductor memory and data storage solutions.
7+ YOEBachelor's in Computer or Electrical Engineering; 7+ years digital circuit design; RTL and gate-level verification; collaboration across multi-functional teams.
RTL, Verilog, Gate-level verification
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Product Development Engineer
San Jose, California, United States
$106k-$154k/yr OnsiteFull Time
Altera
Altera: Manufacturer of field-programmable gate arrays and programmable logic devices.
5+ YOEBachelor's or Master's in Electrical Engineering (or related) with 5+ years industry experience in IC design/test, DFT/ATPG/MBIST/IJTAG/JTAG, RTL design/synthesis/verification, scripting (Python/Perl/TCL), and semiconductor manufacturing test.
Python, Perl, TCL, ATPG, MBIST, IJTAG, JTAG, RTL, Secure Device Manager (SDM)
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