2mo
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RTL Power Analysis Engineer
Austin, Texas, United States
$127k-$217k/yr HybridFull Time
Bachelor or Masters in Electrical Engineering or Computer Science; strong RTL power reduction experience; power analysis tools proficiency.
Ptpx, Power Artist, RTL design, Python
3mo
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RTL Design Engineer
Austin, Texas, United States
OnsiteFull Time
Bachelor's degree in Electrical Engineering; experience with RTL design, Verilog/SystemVerilog, DSP, and mixed-signal/analog integration.
Verilog, SystemVerilog, DSP, Scripting (Python, Perl), Synthesis, Verification, DFT, Lint tools
3mo
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RTL Design Engineer
Austin or Phoenix or Hillsboro
$106k-$200k/yr OnsiteFull Time
2+ YOEBachelor’s or Master’s in Electrical/Computer Engineering with 2+ years experience; knowledge of RTL design, Verilog/SystemVerilog, and basic digital design.
Verilog, SystemVerilog, VHDL, Design Compiler, Genus, Python, Perl, TCL, ModelSim, VCS, Xcelium, UVM, OVM
3mo
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Senior RTL Engineer/Lead
Austin, Texas, United States
$152k-$255k/yr OnsiteFull Time
8+ YOE8+ years RTL design experience for complex IP/CPU subsystems, strong SystemVerilog/Verilog and synthesis skills, front-end quality flow knowledge, scripting (Perl/Python/Tcl), and collaboration with DV/DFT/PD teams.
SystemVerilog, Verilog, Perl, Python, Tcl, Lint, CDC, LEC
1mo
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Principal RTL Methodology Architect
Austin, Texas, United States
HybridFull Time
10+ YOEBS/MS in EE/CS or similar with 10+ years experience; deep RTL/SystemVerilog/Verilog expertise; experience with RTL methodology, IP reuse, linting and static analysis (SpyGlass, VC Lint), frontend EDA flows, Python and CI/CD; strong communication.
SystemVerilog, Verilog, SpyGlass, Synopsys VC SpyGlass, VC Lint, VCS, Xcelium, Questa, Python, CI/CD, UPF
1mo
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RTL Feasibility Engineer, AI/ML Processors
Austin, Texas, United States
$99k-$148k/yr OnsiteFull Time
Bachelor's in science/engineering required. Strong Python, Perl, Shell scripting; familiarity with SystemVerilog and RTL; experience with Git; experience in logic design, synthesis, timing and power analysis; strong communication and collaboration skills.
Python, Perl, Shell, SystemVerilog, RTL, Git, digital design simulator, design synthesis engine, power estimation engine
2mo
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Sr. Engineer, RTL Implementation
Austin or Santa Clara
$100k-$500k/yr HybridFull Time
Experienced in high-performance physical design; RTL coding (Verilog/VHDL); synthesis/place-and-run; CPU micro-architecture.
Verilog, VHDL, Synthesis tools, Place and Route tools
1mo
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RTL Design and Architect lead
San Jose or Austin
OnsiteFull Time
10+ YOE10+ years industry experience, Bachelor's/Master's in Electronics/Electrical Engineering, SOC project leadership, RTL design with VHDL/Verilog/SystemVerilog, strong digital design fundamentals, exposure to micro-processor integration and high-speed peripherals, Python familiarity.
VHDL, Verilog, SystemVerilog, Python, GDSII, DDR, PCIe, UCIe, Ethernet
1mo
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Principal RTL Methodology Architect (767547)
Austin, Texas, United States
HybridFull Time
10+ YOE10+ years experience with SystemVerilog/Verilog RTL design, RTL methodology and signoff (lint, CDC, static analysis), EDA simulators, IP reuse, UPF low-power flows, Python automation and CI/CD; BS/MS in EE/CS.
SystemVerilog, Verilog, SpyGlass, Synopsys VC SpyGlass, VC Lint, VCS, Xcelium, Questa, Python, CI/CD, UPF, CDC
2mo
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Sr. RTL Design Engineer (Silicon Engineering)
Austin or Irvine or Redmond or Sunnyvale
$170k-$235k/yr OnsiteFull Time
5+ YOEBachelor’s in electrical/computer engineering or computer science; 5+ years of RTL implementation experience.
Verilog, SystemVerilog, Python, EDA tools, HDL simulators, HDL Lint
2mo
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Lead RTL Design Engineer
Austin or Pittsburgh or San Jose
$160k-$250k/yr OnsiteFull Time
8+ YOE8+ years RTL design with tape-out ownership; SystemVerilog; on-chip networks, memory subsystems, NoC; low-power design; DV collaboration; silicon bring-up.
SystemVerilog, UPF, AXI, AHB, APB, TileLink, NoC, SDC, STA, ATPG, DFT, memory compiler
6d
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Sr. Staff SoC RTL Engineer
Austin, Texas, United States
OnsiteFull Time
8+ YOEBachelors in EE/CE (or higher),8+ years ASIC/SoC RTL design,strong Verilog/SystemVerilog skills,ARM/AMBA experience,front-end ASIC flow knowledge,experience with tapeout/silicon bring-up,and US work authorization.
Verilog, SystemVerilog, ARM, AMBA, AHB, APB, AXI, LINT, CDC, RDC, UPF, FPGA
1mo
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Senior Engineer, GPU RTL Design
Austin or San Jose
$124k-$208k/yr OnsiteFull Time
4+ YOEMaster’s in Electrical/Computer Engineering required for senior/staff; Senior requires 4+ years. Requires RTL design experience (Verilog/SystemVerilog), ASIC front-end flow familiarity, microarchitecture knowledge, and ability to access export-controlled information.
Verilog, SystemVerilog
1w
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Principal PCIe Subsystem RTL lead
San Jose or Santa Clara or Austin or Seattle or Boston
HybridFull Time
10+ YOE10+ years digital IC design experience with 4+ years PCIe subsystem design/integration, strong SystemVerilog RTL skills, experience integrating PCIe controller/SerDes PHY, multi-clock-domain design, and ability to lead architectural work.
SystemVerilog, UVM, PCIe, CXL, SerDes
2mo
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Member of Technical Staff, Hardware, RTL Design Engineer
Palo Alto or Austin
$200k-$420k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE and 5+ years industry experience with advanced process nodes (7nm or below); strong RTL, synthesis, physical design, and timing tool experience; expertise in computer architecture and silicon delivery.
System Verilog, VCS, Verdi, Fusion Compiler, PrimeTime, C, C++, python, ISA assembly, PCIe, UCIe, HBM, DDR, AXI, CHI, Static Timing Analysis (STA)
4w
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Staff RTL Design Engineer - CPU LS/PF/MMU
Santa Clara or Austin
$179k-$219k/yr OnsiteFull Time
3+ YOEBS/MS in CS/CE/EE or equivalent, 3+ years design experience, CPU RTL design experience, proficiency in Verilog/System Verilog/VHDL, strong software engineering (OOP, functional, TDD), verification skills (SVA, coverage).
Chisel, FIRRTL, Verilog, System Verilog, VHDL, Scala, Bluespec, RISC-V, Git/Github, Jira, Confluence, SVA
1mo
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Software R&D Engineer, RTL Optimization Tools
Santa Clara or Austin
$136k-$219k/yr HybridFull Time
3+ YOEMS/PhD in EE or CS (or equivalent experience), 3+ years CAD/VLSI experience, strong C++ and algorithm development, familiarity with RTL (Verilog/SystemVerilog), EDA techniques, and ML techniques for analysis and optimization.
C++, Verilog, SystemVerilog, Verific, Espresso, SAT solvers, LLMs, GNNs, GANs
1mo
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Software R&D Engineer, RTL Optimization Tools
Santa Clara or Austin
$136k-$219k/yr HybridFull Time
3+ YOEMS/PhD in EE or CS (or equivalent experience), 3+ years CAD software and VLSI experience, strong C++ and algorithm development skills, familiarity with Verilog/SystemVerilog and EDA flows, and strong communication skills.
C++, Verilog, SystemVerilog, Verific, Espresso, SAT solvers, LLMs, GNNs, GANs
1mo
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Principal DFT Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOE5+ years DFT implementation and verification experience including scan architectures, JTAG, memory MBIST, ATPG; Verilog/VHDL RTL knowledge; ability to handle RTL DFT changes, analyze ATPG/DRC reports, and support test pattern bring-up.
RTL, MBIST, ATPG, JTAG, TAP, ATE, Verilog, VHDL, SDF
2mo
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Sr. DFT Design Engineer, AWS Machine Learning Acceleration
Austin, Texas, United States
$159k-$215k/yr OnsiteFull Time
5+ YOE5+ years ASIC/SoC design; DFT, ATPG, JTAG, MBIST; scripting; collaboration with PD/architecture; RTL through silicon experience.
ATPG, JTAG, MBIST, RTL, Python, Perl, Tcl, DFT/SCAN/ATPG tools
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