Grand Prairie • 50 milesRemote · Hybrid · Onsite · Field · All Environments
Grand Prairie • 50 milesRemote · Hybrid · Onsite · Field · All Environments
Grand Prairie • 50 milesRemote · Hybrid · Onsite · Field · All Environments
Grand Prairie • 50 milesRemote · Hybrid · Onsite · Field · All Environments
17 rtl verification engineer jobs at 6 companies in Grand Prairie, TX
1mo
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RTL Design/AMS Verification Engineer
Richardson, Texas, United States
RemoteFull Time
5+ YOE5+ years IC design experience; Verilog RTL design and verification experience; Cadence/Synopsys flows; AMS simulation, synthesis and APR; Bachelor's degree in Electrical Engineering; US work authorization (ITAR) required.
Verilog, Cadence, Synopsys, Python, Perl, Tcl, SKILL
5d
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RTL Design Engineer
Richardson, Texas, United States
HybridFull Time
Bachelor’s or master’s degree in engineering; experienced Verilog/SystemVerilog RTL designer with ASIC/SoC flows, synthesis, verification debug, EDA tools, and cross-functional IC development experience.
Verilog, SystemVerilog, ASIC, SoC, Electronic Design Automation (EDA), CDC, APR
1d
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Sr Design Verification Engineer, HBM Verification Architecture
Richardson, Texas, United States
OnsiteFull Time
4+ YOEBachelor's degree in electrical or computer engineering, 4+ years of verification engineering experience, digital, analog, or mixed-signal verification, and 2+ years in custom or RTL verification flows.
Verilog, FastSpice, Generative AI, AI
2mo
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Staff Design Verification Engineer, HBM Architecture
Richardson, Texas, United States
OnsiteFull Time
7+ YOEBachelor's in EE/CE, 7+ years verification engineering experience (including 5+ years in digital/analog/mixed-signal), 4+ years custom or RTL verification, strong communication and independent verification strategy skills.
Verilog, FastSpice, GenAI, RTL
1w
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Staff Engineer, HBM Verification Architecture
Richardson, Texas, United States
OnsiteFull Time
7+ YOEBachelor’s degree in electrical or computer engineering, 7+ years of verification experience, 5+ years in digital, analog, or mixed-signal verification, and 4+ years in custom or RTL verification flows.
Verilog, FastSpice, GenAI, AI, JEDEC, HBM, DRAM, RTL, SoC, TSV
1w
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Staff Engineer, HBM Verification Architecture
Richardson, Texas, United States
OnsiteFull Time
7+ YOEBachelor's degree in electrical or computer engineering, 7+ years of verification experience, digital, analog, or mixed-signal verification expertise, and 4+ years in custom or RTL design verification flows.
Verilog, FastSpice, GenAI, JEDEC
3mo
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Sr Design Verification Engineer/Architect, HBM
Richardson, Texas, United States
OnsiteFull Time
4+ YOEBachelor's degree in Electrical or Computer Engineering; 4+ years verification experience; strong in digital, analog, or mixed-signal verification; 2+ years in custom RTL/design verification.
Verilog, FastSpice, Co-simulation
2mo
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Staff Design Verification Engineer, HBM Architecture
Richardson, Texas, United States
OnsiteFull Time
7+ YOEBachelor's in EE/CE, 7+ years verification experience (incl. 5+ years digital/analog/mixed-signal), 4+ years custom or RTL verification, strong communication and ability to define verification strategy.
Verilog, FastSpice
2mo
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Sr Design Verification Engineer/Architect, HBM
Richardson, Texas, United States
OnsiteFull Time
4+ YOEBachelor's in EE/CE or related, 4+ years verification experience (digital/analog/mixed-signal), 2+ years custom or RTL verification, Verilog/FastSpice experience, strong problem-solving and communication skills.
Verilog, FastSpice, GenAI, RTL2GDS, JEDEC
2mo
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DFT Engineer (Design for Testability) - Staff
Richardson, Texas, United States
OnsiteFull Time
5+ YOEBachelor's/Master's in EE/CE or equivalent, strong digital design and DFT fundamentals (scan, MBIST, JTAG), RTL experience (SystemVerilog/VHDL), familiarity with semiconductor test flows, and 5+ years DRAM or ASIC DFT design/verification experience.
SystemVerilog, VHDL, RTL, JTAG, MBIST
2mo
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Digital IC Design Engineer | Custom
Dallas, Texas, United States
OnsiteFull Time
8+ YOEBachelor's in EE/ECE/Computer Engineering, 8 years engineering experience including 3 years mixed-signal design verification, experience with Gates+SDF timing verification, automation scripting, and mixed-signal verification flows.
JasperGold, Gates+SDF, RTL, STA
5d
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Senior Digital Design Engineer, HBM
Richardson, Texas, United States
OnsiteFull Time
Design digital logic across RTL implementation, verification, timing, low-power methodologies, and post-silicon debug using Verilog/SystemVerilog and related design analysis tools.
Verilog, SystemVerilog, AI-Enabled tools, CPF, UPF, SDC, ATPG
3w
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Senior Staff Digital Design Engineer
Plano, Texas, United States
HybridFull Time
5+ YOE5+ years in digital IC design with Verilog/SystemVerilog, RTL, synthesis, STA, verification, silicon debug, UVM and experience with industry EDA tools; B.Tech/M.Tech in electronics or related field.
Verilog/SystemVerilog, UVM, I²C, I3C, SPI, UART, Python, Tcl, Perl, Shell, Xcelium, Genus, SpyGlass, OneSpin/JasperGold, Innovus, PrimeTime/Tempus, DFT, ARM, AMBA (AXI/AHB/APB), Cadence Virtuoso, STA, LEC, Lint, Formal Verification
2mo
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Non-Volatile Memory Circuit Design Engineer
Richardson, Texas, United States
RemoteFull Time
10+ YOE10+ years NVM circuit design experience; Cadence/Synopsys flow; RTL design/verification; EE degree; remote option depending on skills.
Cadence, Synopsys, RTL design tools, PERL, Python, TCL, SKILL
1mo
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Digital IC Design Engineer
Dallas, Texas, United States
OnsiteFull Time
1+ YOEBachelor's in EE/CE or related; 1+ years digital IC design experience; proficiency in RTL (Verilog/SystemVerilog), functional verification, synthesis/static timing, low-power techniques; exposure to SPI/I2C/UART; scripting (Python, Tcl, Perl).
Verilog, SystemVerilog, Synopsys Design Compiler, Cadence Genus, Python, Tcl, Perl
2mo
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Principal Engineer DSP PHY Digital Design
Dallas, Texas, United States
HybridFull Time
10+ YOEB.S. +10 yrs or M.S. +7 yrs in EE/CE or related; strong digital communications/DSP fundamentals; experience with high-speed wireline DSP (FFE/DFE, CDR, FEC), RTL design/verification; C++, MATLAB proficiency.
C++, MATLAB, Python
2mo
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Staff Wireless IC Digital Designer
Dallas, Texas, United States
OnsiteFull Time
8+ YOESenior level design engineer with 8-12 years in digital RF/wireless design, IC/SoC development, RTL, and verification.
RTL, Synthesis, STA, ATPG, RFIC, SoC, Digital design, FPGA design
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