New Braunfels • 50 milesRemote · Hybrid · Onsite · Field · All Environments
New Braunfels • 50 milesRemote · Hybrid · Onsite · Field · All Environments
New Braunfels • 50 milesRemote · Hybrid · Onsite · Field · All Environments
New Braunfels • 50 milesRemote · Hybrid · Onsite · Field · All Environments
71 rtl verification engineer jobs at 28 companies in New Braunfels, TX
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Senior Firmware Verification Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOEBS/MS in EE or Computer Engineering required; 5+ years firmware verification experience in pre-silicon; SystemVerilog, C, Python/Perl skills; familiarity with RTL, emulation, and lab test equipment.
SystemVerilog, UVM, C, Python, Perl, RTL, FPGA, QEMU, SimVision, Verdi, oscilloscopes, power supplies, logic analyzers
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CPU Core RTL Design Engineer
Austin, Texas, United States
HybridFull Time
Design and implement CPU core RTL, contribute to microarchitecture, collaborate with verification and physical design, and debug pre/post-silicon issues; Bachelor’s+ in EE/CE preferred.
Verilog, SystemVerilog, Python, Tcl
2w
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ASIC SoC Verification Engineer (788438)
Austin, Texas, United States
HybridFull Time
Experience in SoC/IP/SubSystem verification, SystemC/TLM and RTL environments, hardware emulation, knowledge of high-speed interfaces, strong problem-solving and communication;BS required, MS preferred.
SystemC/TLM, RTL, hardware emulation
2w
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ASIC SoC Verification Engineer
Austin, Texas, United States
OnsiteFull Time
Experience in SoC/IP/Subsystem verification, SystemC/TLM and RTL verification, hardware emulation familiarity, strong problem-solving and communication; BS required (MS preferred).
SystemC, TLM, RTL, hardware emulation
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Senior ASIC Verification Engineer
Austin, Texas, United States
$136k-$265k/yr OnsiteFull Time
3+ YOE3+ years relevant experience, Bachelor's/Master's in Computer or Electrical Engineering (or equivalent), proficiency in System Verilog, UVM, Python, Verilog, RTL, and familiarity with VCS and Verdi.
System Verilog, UVM, Python, Verilog, RTL, VCS, Verdi
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ASIC Verification Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOE5+ years verification experience, 2+ full block/system verification cycles, deep VLSI verification knowledge, experience with SystemVerilog/UVM/eRM, familiarity with data-paths/protocols (Ethernet preferred), mentoring and cross-team collaboration.
SystemVerilog, UVM, eRM, RTL, Ethernet
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Principal Design Verification Engineer (Silicon Engineering)
Austin or Irvine or Redmond or Sunnyvale
OnsiteFull Time
10+ YOEBachelor’s in electrical/computer engineering or CS; 10+ years in design verification/test benches; UVM/OVM/VMM; RTL design; Python scripting; open to extended hours.
UVM, OVM, VMM, Python, RTL design
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Staff RTL Design Engineer - CPU LS/PF/MMU
Santa Clara or Austin
$179k-$219k/yr OnsiteFull Time
3+ YOEBS/MS in CS/CE/EE or equivalent, 3+ years design experience, CPU RTL design experience, proficiency in Verilog/System Verilog/VHDL, strong software engineering (OOP, functional, TDD), verification skills (SVA, coverage).
Chisel, FIRRTL, Verilog, System Verilog, VHDL, Scala, Bluespec, RISC-V, Git/Github, Jira, Confluence, SVA
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Senior Formal Verification Engineer
Santa Clara or Austin
$136k-$265k/yr OnsiteFull Time
5+ YOE5+ years experience with formal verification of RTL; degree in CS/CE/EE/Mathematics or equivalent experience; experience with Verilog/SystemVerilog, formal tools, abstraction techniques, and scripting (TCL, Perl, Python).
Verilog, SystemVerilog, TCL, Perl, Python
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Digital Design Verification Engineer
Bristol or Austin
£125k/yr OnsiteFull Time
5+ YOE5+ years in digital verification for high-performance ASICs/SoCs; strong SystemVerilog, SVA, UVM, Cocotb, formal verification, CDC/RDC, and algorithm modelling (MATLAB/Simulink or Python/NumPy) skills; experience with high-speed IP (SerDes, DDR/HBM, PCIe).
SystemVerilog, UVM, SVA, CocoTB, MATLAB/Simulink, Python, NumPy, Jasper, FPGA, RTL simulation, formal verification, linting, CDC/RDC, STA, UPF, CPF, gate-level simulation
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ASIC Engineer, Design Verification
Sunnyvale or Austin
$114k-$172k/yr OnsiteFull Time
2+ YOEBachelor's in CS/CE or equivalent,2+ years SystemVerilog/UVM or C/C++ hardware verification, experience with EDA simulation tools and scripting (Python,TCL,Perl,Shell),and RTL debug/root-cause analysis.
SystemVerilog, UVM, C, C++, Python, TCL, Perl, Shell, EDA simulation tools, Emulation
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Staff SoC Power Performance Verification Engineer
Austin, Texas, United States
$198k-$268k/yr HybridFull Time
Requires SoC RTL performance analysis, hardware emulation, emulator bring-up, system-level debugging, memory architecture knowledge, Verilog/SystemVerilog, C/C++, Python or Ruby, and multiprocessor architecture expertise.
RTL, System-on-Chip (SoC), Verilog, SystemVerilog, C, C++, Python, Ruby, Unix, Linux, Git, Subversion, AI, ARM architecture, CPU, GPU, I/O, MMU
1w
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CPU Micro-architect/RTL Designer
Austin, Texas, United States
$212k-$318k/yr OnsiteFull Time
6+ YOEExpertise in CPU microarchitecture, Verilog/VHDL RTL design, timing/power trade-offs, verification, and scripting (Perl/Python). Requires advanced degree and multiple years of engineering experience as listed.
Verilog, VHDL, Perl, Python
3w
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Sr. Formal Verification Engineer, Annapurna Labs
Austin or Cupertino
$159k-$248k/yr OnsiteFull Time
7+ YOEBachelor's in CS/EE,7+ years formal verification experience as IP/block owner, expertise in abstraction and end-to-end checking, RTL and microarchitecture comprehension, and coding/scripting skills.
C, C++, C#, Node.JS, Java, Python, PHP, Ruby
2d
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ASIC Digital Verification Design, Sr Staff Engineer
Austin, Texas, United States
$138k-$208k/yr OnsiteFull Time
8+ YOEBSEE and 8–10+ years of ASIC or SoC verification experience; expertise in SystemVerilog and UVM; protocol knowledge in PCIe, CXL, DDR, or Ethernet; simulator experience and strong debugging skills.
SystemVerilog, UVM, VCS, ModelSim, RTL, PCIe, CXL, DDR, Ethernet
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CPU Core Design Verification Testbench Lead
Austin or Santa Clara
HybridFull Time
8+ YOE8+ years in CPU verification and testbench development; deep hands-on experience with high-performance out-of-order RISC-V cores; CVM/UVM experience; cross-functional debug across RTL, logs, and post-silicon environments; familiarity with AI-assisted verification.
CVM, UVM, Python, C/C++
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Principal DFT Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOE5+ years DFT implementation and verification experience including scan architectures, JTAG, memory MBIST, ATPG; Verilog/VHDL RTL knowledge; ability to handle RTL DFT changes, analyze ATPG/DRC reports, and support test pattern bring-up.
RTL, MBIST, ATPG, JTAG, TAP, ATE, Verilog, VHDL, SDF
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Lead FPGA Design Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOEBachelor’s degree in a related technical field and 5–10 years of FPGA or platform engineering experience. Requires FPGA design, RTL, verification, timing, lab debugging, and digital interface expertise.
FPGA, RTL, AMD/Xilinx, Intel/Altera, SPI, I2C, UART, Ethernet, PCIe, JESD, digital oscilloscopes, logic analyzers, function generators, printed circuit boards (PCBs)
2w
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R&D Engineer IC Design 4
Austin or San Jose
$122k-$195k/yr OnsiteFull Time
6+ YOEDesign and verify RTL/Verilog blocks for ASICs including synthesis, timing closure, formal verification, scripting, and RTL/gate-level power analysis. BS/MS in ECE and 6+ years experience.
Verilog, RTL, TCL, Perl, Synopsys Design Compiler, DC topo, Cadence RTL Compiler, Primetime, liberty (LIB), Synopsys Formality, Cadence Conformal, Spyglass, svn, git
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Firmware Engineer II
Austin, Texas, United States
OnsiteFull Time
Develop bare-metal firmware in C for DDR5 PHY and microcontrollers; debug RTL simulations and silicon bring-up; knowledge of DDR5 JEDEC spec, scripting (Shell/Perl/Python/TCL), and verification EDA tools required.
C, Verilog, microcontrollers, Shell, Perl, Python, TCL, IDE, RTL, simulators, waveform viewers, Verification EDA Tools
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