3mo
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SoC Test Engineer
Austin or Cupertino or San Diego
OnsiteFull Time
10+ YOEBachelor's degree and 10+ years in SoC test engineering with strong programming and hardware test skills.
Teradyne UFlex, ip750, J750, Advantest 93k, Oscilloscope, Logic analyzer, PERL, C/C++, Visual Basic
2mo
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SoC Design Engineer
Austin, Texas, United States
$122k-$232k/yr HybridFull Time
3+ YOEBachelor's in Electrical/Computer Engineering; 3+ years in microarchitecture/RTL design; clock domain crossing, low-power design; RTL tools, SoC integration.
RTL design, SoC integration tools, NoC architectures, Low-power design, Power-area-timing optimization
2mo
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SOC Silicon Design Engineer
Austin or Boxborough
HybridFull Time
Design and develop custom silicon for CG SoC; collaborate across teams; strong analytical and communication skills.
Scripting (Perl, TCL, Python), EDA tools, VLSI design flow, CMOS technology
1d
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ASIC SoC Verification Engineer
Austin, Texas, United States
OnsiteFull Time
Experience in SoC/IP/Subsystem verification, SystemC/TLM and RTL verification, hardware emulation familiarity, strong problem-solving and communication; BS required (MS preferred).
SystemC, TLM, RTL, hardware emulation
1w
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Sr. Staff SoC RTL Engineer
Austin, Texas, United States
OnsiteFull Time
8+ YOEBachelors in EE/CE (or higher),8+ years ASIC/SoC RTL design,strong Verilog/SystemVerilog skills,ARM/AMBA experience,front-end ASIC flow knowledge,experience with tapeout/silicon bring-up,and US work authorization.
Verilog, SystemVerilog, ARM, AMBA, AHB, APB, AXI, LINT, CDC, RDC, UPF, FPGA
1mo
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Senior SoC Performance Verification Engineer
Raleigh or Redmond or Austin
$120k-$235k/yr HybridFull Time
1+ YOEDoctorate/MS/BS in EE/CE/CS (or equivalent) with 1/4/5+ years technical engineering experience respectively; ability to pass Microsoft Cloud Background Check and export-control screening; SoC performance verification and System Verilog/UVM, C/C++ experience preferred.
System Verilog, UVM, C, C++
1w
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Staff Mixed-Signal SOC Engineer – Infrastructure Power
Austin, Texas, United States
HybridFull Time
7+ YOEMSEE or equivalent, 7+ years mixed-signal SoC experience with tapeout-to-production history; deep expertise in analog, digital, verification or system architecture; automated test and silicon validation experience; mentoring ability.
2w
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Custom SOC IP Verification Engineer
Santa Clara or Austin
$168k-$311k/yr OnsiteFull Time
6+ YOEB.S./M.S. in engineering or equivalent experience,6+ years ASIC verification with fabric/interconnect focus,proficient in SystemVerilog and UVM,experience with interconnect protocols and scripting (Python,Perl,TCL).
SystemVerilog, UVM, AMBA AXI, CHI, Python, Perl, TCL, Palladium, Veloce, SystemVerilog Assertions (SVA)
2w
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Custom SOC IP Verification Engineer
Santa Clara or Austin
$168k-$311k/yr OnsiteFull Time
6+ YOE6+ years ASIC verification experience with fabric/interconnect/NoC, strong SystemVerilog and UVM skills, knowledge of interconnect protocols (AMBA AXI, CHI), scripting (Python, Perl, TCL), and degree in computer/electrical engineering or equivalent experience.
SystemVerilog, UVM, AMBA AXI, CHI, Python, Perl, TCL, Palladium, Veloce, SVA
1mo
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SOC Platform Architect
San Diego or Austin
$212k-$318k/yr OnsiteFull Time
6+ YOEBachelor's in EE/CS (Master's/PhD highly desired) with relevant systems engineering experience (6+ years minimum depending on degree); deep SoC/IP or micro-architecture experience; strong modeling and programming skills (C++, Python).
C++, Python, Android, Linux, Windows, Zephyr, FreeRTOS
2mo
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Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Irvine or Austin or Sunnyvale
$160k-$220k/yr OnsiteFull Time
5+ YOEBachelor’s degree in electrical engineering, computer engineering or computer science; 5+ years ASIC/physical design experience; strong EDA tool knowledge; scripting skills; ability to work extended hours.
EDA tools, Python, Csh/Bash/Shell, Perl, TCL, Makefile
1d
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ASIC SoC Verification Engineer (788438)
Austin, Texas, United States
HybridFull Time
Experience in SoC/IP/SubSystem verification, SystemC/TLM and RTL environments, hardware emulation, knowledge of high-speed interfaces, strong problem-solving and communication;BS required, MS preferred.
SystemC/TLM, RTL, hardware emulation
2mo
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SoC Architect, Memory Subsystem
San Jose or Austin
$151k-$252k/yr OnsiteFull Time
6+ YOE6+ years in computer engineering/memory subsystems; strong knowledge of memory hierarchies, interfaces (DDR/LPDDR/HBM), controllers, caches; experience with PPA optimization; collaboration with software/hardware teams.
DDR memory interfaces, LPDDR, HBM, Memory controllers, Cache subsystems, Cache coherence protocols, Bus protocols (CHI, ACE, AXI), Android ecosystem, Arm architecture, Analysis tools
1mo
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Staff Digital Design Engineer – SOC Low Power, Clocking & Integration
Austin, Texas, United States
$143k-$266k/yr HybridFull Time
10+ YOEBS/MS in Electrical Engineering, 10+ years digital CMOS IC design experience, expertise in Verilog/System Verilog, UPF/CPF, AXI/AHB/APB, RTL design, synthesis, timing, power analysis, simulation, scripting (Python/Perl/Tcl), and leading small teams.
Verilog, System Verilog, UPF, CPF, AXI, AHB, APB, RISC-V, C, Python, Perl, Tcl, Perforce, Git, Methodics
13h
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ASIC Engineer, Design
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
6+ YOEBachelor's degree or equivalent,6+ years hardware design experience for production silicon,expertise in microarchitecture,RTL and SoC integration,strong communication and collaboration skills.
RTL, Synthesis, Timing Closure, Formal Verification Methodology, SoC, EMR
2mo
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SOC Top Level Physical Design Engineer, Annapurna Labs
Cupertino or Austin
$159k-$248k/yr OnsiteFull Time
10+ YOEBS + 10 years or MS + 7 years in EE/CS; 5+ years physical verification; experience with backend physical design flows and industry-standard tools.
Calibre, IC Validator, PVS, Innovus, FC
1mo
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Staff Digital Design Engineer – SOC Low Power, Clocking & Integration
Austin, Texas, United States
$143k-$266k/yr HybridFull Time
10+ YOEBS/MS in EE, 10+ years digital CMOS IC design experience, Verilog/System Verilog expertise, low-power (UPF/CPF) and clocking/CDC/RDC knowledge, AXI/AHB/APB experience, scripting (Python/Perl/Tcl), and leadership of small design teams.
Verilog, System Verilog, UPF, CPF, AXI, AHB, APB, C, Python, Perl, Tcl, Perforce, Git, Methodics
1mo
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Principal System Debug Engineer
Austin or Milpitas
OnsiteFull Time
Senior-level experience in system validation and debug for server/rack platforms, strong knowledge of Arm or x86, PCIe and CXL, OS/firmware/device driver/BIOS interactions, SoC and memory subsystems, and ability to lead cross-functional debug efforts.
PCIe, CXL, Arm, x86, Operating Systems, Device Drivers, BIOS, SoC, RAS
2mo
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Principal Design Verification Engineer
Austin or Texas or Santa Clara or Malta
$153k-$290k/yr OnsiteFull Time
8+ YOEBachelor's in engineering, 8+ years design verification (CPU/SoC) experience, hands-on SystemVerilog/UVM and constrained-random verification, scripting in Python/Perl/Shell, familiarity with CPU architectures and cache/coherency concepts.
SystemVerilog, UVM, C, Assembly, Python, Perl, Shell
3w
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Senior Engineer, Security & Compliance (US)
Austin or New York City or San Francisco
$110k-$150k/yr HybridFull Time
5+ YOE5+ years security engineering experience in SaaS/cloud environments; hands-on SOC 2/ISO control implementation, cloud security (GCP/AWS/Azure), SIEM/monitoring, CI/CD automation, and AI/agent security.
GCP, AWS, Azure, SOC 2 Type II, ISO 27001, ISO 42001, SIEM, SAST, DAST, Checkov, tfsec, OPA/Rego, CI/CD
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