212 soc engineer jobs at 51 companies in Burnet, TX
2mo
Save
Mark Applied
Hide
SoC Design Engineer
Austin, Texas, United States
$122k-$232k/yr HybridFull Time
3+ YOEBachelor's in Electrical/Computer Engineering; 3+ years in microarchitecture/RTL design; clock domain crossing, low-power design; RTL tools, SoC integration.
RTL design, SoC integration tools, NoC architectures, Low-power design, Power-area-timing optimization
2mo
Save
Mark Applied
Hide
SOC Silicon Design Engineer
Austin or Boxborough
HybridFull Time
Design and develop custom silicon for CG SoC; collaborate across teams; strong analytical and communication skills.
Scripting (Perl, TCL, Python), EDA tools, VLSI design flow, CMOS technology
2mo
Save
Mark Applied
Hide
SoC QoS/Fabric Performance Engineer, Platform Architecture
Austin, Texas, United States
OnsiteFull Time
Experience with SoC architecture, on-chip interconnects and memory Quality-of-Service; working with hardware and software engineering teams to define platform architecture.
1w
Save
Mark Applied
Hide
ASIC SoC Verification Engineer
Austin, Texas, United States
OnsiteFull Time
Experience in SoC/IP/Subsystem verification, SystemC/TLM and RTL verification, hardware emulation familiarity, strong problem-solving and communication; BS required (MS preferred).
SystemC, TLM, RTL, hardware emulation
2w
Save
Mark Applied
Hide
Sr. Staff SoC RTL Engineer
Austin, Texas, United States
OnsiteFull Time
8+ YOEBachelors in EE/CE (or higher),8+ years ASIC/SoC RTL design,strong Verilog/SystemVerilog skills,ARM/AMBA experience,front-end ASIC flow knowledge,experience with tapeout/silicon bring-up,and US work authorization.
Verilog, SystemVerilog, ARM, AMBA, AHB, APB, AXI, LINT, CDC, RDC, UPF, FPGA
1mo
Save
Mark Applied
Hide
Senior SoC Performance Verification Engineer
Raleigh or Redmond or Austin
$120k-$235k/yr HybridFull Time
1+ YOEDoctorate/MS/BS in EE/CE/CS (or equivalent) with 1/4/5+ years technical engineering experience respectively; ability to pass Microsoft Cloud Background Check and export-control screening; SoC performance verification and System Verilog/UVM, C/C++ experience preferred.
System Verilog, UVM, C, C++
4w
Save
Mark Applied
Hide
SoC Offensive Security Staff Engineer
Austin, Texas, United States
$198k-$268k/yr HybridFull Time
Deep SoC architecture and integration knowledge, adversarial security assessment experience, SystemVerilog/UVM proficiency, firmware analysis (UEFI/uBoot/Trusted Firmware), PoC/exploit development, strong problem solving and communication.
SystemVerilog, UVM, HW Dev IDEs, UEFI, uBoot, MCUBoot, Trusted Firmware, Caliptra, DICE, PCIe, CXL, SMBus, SPI, I2C, UART, AXI, CHI, CXS, APB, ATB, LPI
2w
Save
Mark Applied
Hide
Staff Mixed-Signal SOC Engineer – Infrastructure Power
Austin, Texas, United States
HybridFull Time
7+ YOEMSEE or equivalent, 7+ years mixed-signal SoC experience with tapeout-to-production history; deep expertise in analog, digital, verification or system architecture; automated test and silicon validation experience; mentoring ability.
3w
Save
Mark Applied
Hide
Custom SOC IP Verification Engineer
Santa Clara or Austin
$168k-$311k/yr OnsiteFull Time
6+ YOEB.S./M.S. in engineering or equivalent experience,6+ years ASIC verification with fabric/interconnect focus,proficient in SystemVerilog and UVM,experience with interconnect protocols and scripting (Python,Perl,TCL).
SystemVerilog, UVM, AMBA AXI, CHI, Python, Perl, TCL, Palladium, Veloce, SystemVerilog Assertions (SVA)
3w
Save
Mark Applied
Hide
Custom SOC IP Verification Engineer
Santa Clara or Austin
$168k-$311k/yr OnsiteFull Time
6+ YOE6+ years ASIC verification experience with fabric/interconnect/NoC, strong SystemVerilog and UVM skills, knowledge of interconnect protocols (AMBA AXI, CHI), scripting (Python, Perl, TCL), and degree in computer/electrical engineering or equivalent experience.
SystemVerilog, UVM, AMBA AXI, CHI, Python, Perl, TCL, Palladium, Veloce, SVA
1mo
Save
Mark Applied
Hide
SOC Platform Architect
San Diego or Austin
$212k-$318k/yr OnsiteFull Time
6+ YOEBachelor's in EE/CS (Master's/PhD highly desired) with relevant systems engineering experience (6+ years minimum depending on degree); deep SoC/IP or micro-architecture experience; strong modeling and programming skills (C++, Python).
C++, Python, Android, Linux, Windows, Zephyr, FreeRTOS
4d
Save
Mark Applied
Hide
Datacenter Compute SoC Architect
San Jose or San Diego or Portland or Austin
$211k-$356k/yr OnsiteFull Time
10+ YOE10+ years SoC/compute architecture experience, 3+ years in datacenter/server SoCs; Bachelor’s degree in EE/CE/CS; expertise in CPU/memory/Interconnect, PCIe/CXL, and performance modeling.
C++, SystemC, UCIe, PCIe, CXL, ARM AMBA CHI, AXI
2mo
Save
Mark Applied
Hide
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Irvine or Austin or Sunnyvale
$160k-$220k/yr OnsiteFull Time
5+ YOEBachelor’s degree in electrical engineering, computer engineering or computer science; 5+ years ASIC/physical design experience; strong EDA tool knowledge; scripting skills; ability to work extended hours.
EDA tools, Python, Csh/Bash/Shell, Perl, TCL, Makefile
1w
Save
Mark Applied
Hide
ASIC SoC Verification Engineer (788438)
Austin, Texas, United States
HybridFull Time
Experience in SoC/IP/SubSystem verification, SystemC/TLM and RTL environments, hardware emulation, knowledge of high-speed interfaces, strong problem-solving and communication;BS required, MS preferred.
SystemC/TLM, RTL, hardware emulation
2mo
Save
Mark Applied
Hide
SoC Architect, Memory Subsystem
San Jose or Austin
$151k-$252k/yr OnsiteFull Time
6+ YOE6+ years in computer engineering/memory subsystems; strong knowledge of memory hierarchies, interfaces (DDR/LPDDR/HBM), controllers, caches; experience with PPA optimization; collaboration with software/hardware teams.
DDR memory interfaces, LPDDR, HBM, Memory controllers, Cache subsystems, Cache coherence protocols, Bus protocols (CHI, ACE, AXI), Android ecosystem, Arm architecture, Analysis tools
1d
Save
Mark Applied
Hide
Physical Design - SOC Top Lead
San Jose or Pittsburgh or Austin
$200k-$250k/yr OnsiteFull Time
8+ YOEEnd-to-end SOC top ownership including full-chip integration, timing closure, power/PDN analysis, physical verification, SI, clock/reset, DFT, package co-design, and tapeout readiness; advanced degree in EE and extensive PD experience.
Innovus, ICC2, Tempus, PrimeTime, RedHawk, Calibre, Voltus, TCL, shell, python
1w
Save
Mark Applied
Hide
Principal System Architect RF SoC - TeraWave
San Diego or California or Austin or Texas or Kent or Seattle
$269k-$377k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
10+ YOE10+ years RF systems design experience, Bachelor’s in EE/CE or related, networking/MAC/PHY/DSP experience, Matlab/System C/C/C++ proficiency, knowledge of DSP and communications (OFDM,QPSK,QAM), ASIC/FPGA lifecycle experience preferred.
Matlab, System C, C/C++
1w
Save
Mark Applied
Hide
ASIC Engineer, Design
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
6+ YOEBachelor's degree or equivalent,6+ years hardware design experience for production silicon,expertise in microarchitecture,RTL and SoC integration,strong communication and collaboration skills.
RTL, Synthesis, Timing Closure, Formal Verification Methodology, SoC, EMR
1mo
Save
Mark Applied
Hide
Staff Digital Design Engineer – SOC Low Power, Clocking & Integration
Austin, Texas, United States
$143k-$266k/yr HybridFull Time
10+ YOEBS/MS in Electrical Engineering, 10+ years digital CMOS IC design experience, expertise in Verilog/System Verilog, UPF/CPF, AXI/AHB/APB, RTL design, synthesis, timing, power analysis, simulation, scripting (Python/Perl/Tcl), and leading small teams.
Verilog, System Verilog, UPF, CPF, AXI, AHB, APB, RISC-V, C, Python, Perl, Tcl, Perforce, Git, Methodics
2mo
Save
Mark Applied
Hide
SOC Top Level Physical Design Engineer, Annapurna Labs
Cupertino or Austin
$159k-$248k/yr OnsiteFull Time
10+ YOEBS + 10 years or MS + 7 years in EE/CS; 5+ years physical verification; experience with backend physical design flows and industry-standard tools.
Calibre, IC Validator, PVS, Innovus, FC
Explore Jobs