3mo
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SoC Test Engineer
Austin or Cupertino or San Diego
OnsiteFull Time
10+ YOEBachelor's degree and 10+ years in SoC test engineering with strong programming and hardware test skills.
Teradyne UFlex, ip750, J750, Advantest 93k, Oscilloscope, Logic analyzer, PERL, C/C++, Visual Basic
3mo
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SoC Design Engineer
Santa Clara, California, United States
$157k-$160k/yr OnsiteFull Time
Master’s in Electrical or Computer Engineering; ASIC/SoC design experience; RTL/verification; EDA tools; programming (Python/C++/Perl).
Verilog, SystemVerilog, PrimeTime, Cadence Virtuoso, Design Compiler, Simvision, Python, C++, Perl, SVA, HLS, EDA Tools
1mo
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Senior SOC Design Engineer
Santa Clara, California, United States
$136k-$265k/yr HybridFull Time
3+ YOEBS/MS in Computer or Electrical Engineering (or equivalent), 3+ years chip design experience focused on SoC integration and automation; expertise in RTL, SOC integration, design automation; scripting with Perl or Python; strong analytical and communication skills.
Perl, Python, RTL, EDA tools
2mo
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SoC Platform Engineer
Saratoga, California, United States
$150k-$220k/yr OnsiteFull Time
Experience with IP integration, system verification, firmware for SoC; RTL, AMBA interconnects; C/Python scripting; ARM architecture.
SystemVerilog, VHDL, UVM, C, Python, Tcl, Bash, Makefiles, Git, VCS, Questa, Xcelium, JTAG
1mo
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SOC Intergration Engineer
Mountain View, California, United States
$120k-$600k/yr HybridFull Time
SystemVerilog; Python/Perl; experience integrating CPUs/GPUs/accelerators; SOC RTL; timing constraints; DV automation; emulation/verification familiarity.
SystemVerilog, Python, Perl, RTL design, DV tooling, Synthesis
2d
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SoC Verification Engineer
Austin or Santa Clara or Hillsboro
$142k-$200k/yr HybridFull Time
3+ YOE3+ years SoC design verification experience (4+ with bachelor's) with OVM/UVM, AMBA protocols, UVM testbench creation, debugging, and test planning; bachelor's or master's in EE/CE/CS or related.
OVM, UVM, CHI, AXI, AHB, APB, VIP, emulation models, system simulation tools
4w
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SOC IP Methodology Engineer - Custom SOC
Santa Clara or Austin or Hillsboro
$168k-$311k/yr OnsiteFull Time
8+ YOEMasters (8+ yrs) or BS (10+ yrs) with deep RTL-to-GDS methodology and physical design expertise, experience with EDA tool flows, IP ecosystems, customer-facing SOC development, DFT/BIST, synthesis/CTS/power/PNR, and scripting (Python/Perl/Tcl).
RTL-to-GDSII, Cadence, Synopsys, Mentor, Genus, First Encounter, Innovus, Design Compiler, Fusion Compiler, ICC2, PT-SI, Tempus, Redhawk, IP-XACT, Python, Perl, Tcl
3w
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SoC DFT Engineer, Cloud
Sunnyvale, California, United States
$163k-$237k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE/CS or equivalent; 5+ years DFT architecture/implementation/verification for SoCs; silicon bring-up and test methodology experience (ATE, MBIST, JTAG, SLT); familiarity with fault models and EDA DFT tools; Master's/PhD and 10+ years preferred.
ATE, MBIST, JTAG, System Level Test (SLT), Synopsys, Design Compiler, DFT Max, Siemens EDA, Tessent, TestKompress, IEEE 1149.1, IEEE 1687, BSDL, STIL, ATPG, iJTAG, TAP
3mo
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SOC Architect
Santa Clara or Cambridge or France or Oregon or Boston
$254k-$311k/yr OnsiteFull Time
10+ YOEMS or PhD in Computer Science / Computer Architecture; 10+ years in SoC architecture; 5+ years in engineering teams; experience in SoC design flow, architecture, and performance modeling; CPU architectures, power management, platform hardware, OS, drivers, and firmware.
1mo
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Senior Engineer, SoC Architecture – Memory Subsystem and Interconnect
Mountain View, California, United States
$159k-$218k/yr OnsiteFull Time
7+ YOEBSc/Masters/PhD in CS/Engineering (or equivalent), >7 years experience in fabric/system cache/DRAM controller architecture, 3+ years in SoC/ASIC design, knowledge of memory controllers, ARM bus protocols, JEDEC memory standards.
BookSim Simulator, Platform Architect, ARM, ACE, AXI, AHB, JEDEC, LPDDR, DDR, HBM
3mo
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SR ASIC SoC Design Engineer
Santa Clara, California, United States
$175k-$300k/yr OnsiteFull Time
Senior SoC/ASIC design engineer with experience in embedded subsystems, AI networking ASICs, chiplet-based SoCs, RTL design, and cross-functional collaboration.
SystemVerilog, Verilog, PCIe, NoCs, AMBA protocols (AXI/AHB/APB), CSR generation frameworks, RTL, Synthesis, Emulation, FPGA, SoC IP generation and configuration tools
4w
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SoC Architect
Santa Clara, California, United States
$175k-$265k/yr HybridFull Time
d-Matrix: Develops high-performance semiconductor chips for generative AI inference.
5+ YOEMS in CS/ECE or related with 5+ years in SoC/compute architecture; expert in AI SoC architecture, performance modeling, ML (transformer/CNN/RNN), workload analysis; strong Python; C/C++ preferred; leadership in architecture delivery.
Python, C, C++
1w
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Lead SoC Verification Engineer
Los Altos, California, United States
OnsiteFull Time
Anodize: Developing next-generation personal computing hardware and consumer electronics.
10+ YOE10+ years verifying complex ASICs; BS/MS in EE or CE; deep knowledge of AMBA interconnects; fluent in SystemVerilog/SystemC and UVM; UPF and multi-power-domain verification experience; proven silicon bring-up track record.
SystemVerilog, SystemC, UVM, AMBA CHI, AMBA AXI, AXI-S, APB, UPF
3mo
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SOC Architect
San Francisco, California, United States
$266k-$445k/yr OnsiteFull Time
Define architecture for custom SoCs; lead hardware/software co-design; deep AI/ML accelerator knowledge; cross-functional leadership.
RTL, ASIC, SoC design, edge AI
6d
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SOC Verification and Methodology Engineer - SCL
Santa Clara, California, United States
$153k-$230k/yr OnsiteFull Time
2+ YOEDevelop and implement SOC verification methodologies, create and execute test plans, debug issues; requires SystemVerilog/UVM experience and design verification background.
SystemVerilog, UVM, Perl, Python
1mo
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Lead SoC Architect - India
Sunnyvale or India
OnsiteFull Time
10+ YOERequires Bachelor's or Master's in EE/CE/CS, 10+ years SoC/ASIC experience, expertise in SoC subsystems (CPU/GPU/NPU, NoC, memory, PCIe), C/C++/SystemC modeling, RTL knowledge, and on-site presence in Sunnyvale.
C, C++, SystemC, Linux
1mo
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AI SOC Architect
Los Altos, California, United States
OnsiteFull Time
10+ YOEBachelor's in EE/CE (Master's preferred), 10+ years SoC/compute architecture experience with RISC-V and AI acceleration, expertise in multicore clusters, memory hierarchies, performance modeling, and strong communication skills.
RISC-V, AXI, UALINK, HBM, RTL
2w
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Principal SoC Architect
Walnut Creek, California, United States
$168k-$300k/yr OnsiteFull Time
12+ YOEBachelor's in EE/CE,12+ years ARM CPU SoC/ASIC architecture experience, Ethernet/PCIe and memory subsystem expertise, EM/thermal tradeoff and IP selection experience, scripting in Tcl/Perl/Python preferred.
Tcl, Perl, Python
1w
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Principal SoC Circuit Architect
Mountain View or Sacramento
$143k-$275k/yr HybridFull Time
8+ YOEAdvanced degree or equivalent experience in electrical/computer engineering, 8+ years SoC circuit architecture experience, expertise in high-speed IO PHY, PLL/clocking, signal and power integrity, ability to pass security and export-control screenings.
1mo
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Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Irvine or Austin or Sunnyvale
$160k-$220k/yr OnsiteFull Time
5+ YOEBachelor’s degree in electrical engineering, computer engineering or computer science; 5+ years ASIC/physical design experience; strong EDA tool knowledge; scripting skills; ability to work extended hours.
EDA tools, Python, Csh/Bash/Shell, Perl, TCL, Makefile
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