193 digital design engineer jobs at 86 companies in Hercules, CA
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Senior Digital Design Engineer
Santa Clara or Austin or Redmond
$136k-$265k/yr OnsiteFull Time
5+ YOE5+ years experience in digital/ASIC design, degree in EE/CE or equivalent, experience with high-speed protocols (NVLink, PCI-Express, Ethernet, UCIE), RTL implementation, and ASIC design flows.
NVLink, PCI-Express, Ethernet, UCIE, RTL
1mo
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Digital Layout Design Engineer
Santa Clara, California, United States
OnsiteFull Time
Design custom digital macros and libraries for ASICs at advanced technology nodes; collaborate with integration, CAD, circuit, and technology engineering teams.
1mo
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AI Silicon, Digital Design Engineer
Palo Alto, California, United States
OnsiteFull Time
8+ YOEB.S. or M.S. in EE/Computer Engineering, 8+ years ASIC/SoC digital design experience, Verilog RTL expertise, EDA tool proficiency, synthesis/timing/LEC experience, and mentorship/communication skills.
Verilog, RTL, EDA tools, Logical Equivalence Checking (LEC), Clock Domain Crossing (CDC), Reset Domain Crossing (RDC)
4w
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Machine Learning Digital Design Engineer
Sunnyvale, California, United States
$178k-$250k/yr OnsiteFull Time
8+ YOEBachelor's degree or equivalent, 8+ years hardware design experience for production silicon, expertise in digital µarchitecture, RTL coding, micro-architecture development, and cross-functional technical communication.
RTL, SoC, ASIC, DSP, microcontrollers
3w
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Digital IC Design Engineer | BCP
Santa Clara, California, United States
$130k-$241k/yr OnsiteFull Time
3+ YOEB.S. in Electrical Engineering, 3+ years digital design experience; RTL/Verilog/SystemVerilog, Cadence, Python, UVM, and GDSII experience preferred; ability to implement and verify synthesizable RTL to GDSII.
RTL, Verilog/Systemverilog, Cadence, Python, UVM, VAMS, GDSII
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Senior Digital Design Engineer
Santa Clara or Austin or Redmond
$136k-$265k/yr OnsiteFull Time
5+ YOEBachelors or Master's in EE/CE or equivalent experience, 5+ years relevant experience, experience with high-speed protocols (NVLink, PCI-Express, Ethernet, UCIE), delivering high-bandwidth datapath blocks, deep ASIC design flow knowledge.
NVLink Fusion, NVLink, PCI-Express, Ethernet, UCIE, RTL, SoC
1mo
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Technical Staff Engineer - Digital Design
San Jose, California, United States
$70k-$143k/yr HybridFull Time
12+ YOEBachelor's in EE/CE, 12+ years relevant experience (10+ in FPGA/ASIC IP and system design), VHDL/Verilog expertise, FPGA design/verification experience, strong digital design and architecture knowledge, excellent communication; US citizenship or permanent residency required.
VHDL, Verilog, Libero, Quartus, Vivado, Identify Debugger, SignalTap, ChipScope, ModelSim, QuestaSim, Python, TCL
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PMTS ASIC Digital Design IP ENGINEERING
Santa Clara, California, United States
$167k-$275k/yr OnsiteFull Time
12+ YOEBachelor's or master's degree in electrical or computer engineering, 12+ years of processor or complex SoC digital design, expert Verilog/SystemVerilog, and expertise in microarchitecture, synthesis, timing, CDC, RDC, and low-power design.
Verilog, SystemVerilog, RISC-V, ARM, MIPS, ARC, ISO 26262, DO-254, EDA
2d
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PMTS ASIC Digital Design IP ENGINEERING
Santa Clara, California, United States
$167k-$275k/yr OnsiteFull Time
12+ YOEBachelor's or master's degree in electrical or computer engineering; 12+ years in processor, CPU, DSP, or complex SoC digital design; expert Verilog/SystemVerilog and processor microarchitecture expertise.
Verilog, SystemVerilog, EDA
2w
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Distinguished Engineer, Digital IC Design
Santa Clara, California, United States
$210k-$314k/yr OnsiteFull Time
15+ YOEMaster's required (Ph.D. preferred),15+ years experience in uLED/uVCSEL, ASIC architecture, chiplet and multi-die design, demonstrated leadership, patents/publications, system integration expertise.
2w
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Senior Staff Engineer, Digital IC Design
Santa Clara, California, United States
$134k-$201k/yr OnsiteFull Time
5+ YOEDegree in computer or electrical engineering with 3–5+ years SOC/SoC experience, RTL design in SystemVerilog, SoC integration and timing closure, CDC/clock/reset design, and scripting with Python or Tcl.
SystemVerilog, Python, Tcl
2d
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Senior RTL Design Engineer, Digital Signal Processing
Sunnyvale, California, United States
$163k-$236k/yr OnsiteFull Time
8+ YOEBachelor's degree in electrical or computer engineering, 8 years of DSP or high-speed digital logic design, and experience with communication systems, PHY, MATLAB, Python, or C++.
MATLAB, Python, C++, Design Compiler, Genus, PrimeTime, Tempus, Spyglass, Conformal, SerDes, SystemC
3w
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Senior Digital Product Designer, Design Systems
Milpitas, California, United States
$121k-$206k/yr HybridFull Time
6+ YOE6+ years product design with 2+ years in design systems, expertise in design tokens/component architecture, accessibility-first approach, experience partnering with engineers, advanced Figma skills, Bachelor's in design/HCI or related.
Figma
1d
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Design Engineer III
Menlo Park or Sunnyvale
$140k-$150k/yr HybridFull Time
5+ YOERequires a BS in electrical/computer engineering or computer science, 5+ years of experience, SystemVerilog/UVM verification, coverage and SVA, RTL debug, simulators, Python or Perl, and digital design fundamentals.
SystemVerilog, UVM, VCS, Xcelium, Questa, Verdi, Python, Perl, PrimeTime PX (PTPX), PrimePower, UPF, Palladium, Zebu, RTL-to-GDSII
2mo
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SoC Design Engineer
Santa Clara, California, United States
$157k-$160k/yr OnsiteFull Time
1+ YOEMaster's in Electrical or Computer Engineering required, 1+ year digital design experience; RTL/Verilog, SystemVerilog/SVA, Python, Perl; experience with Synopsys PrimeTime, Cadence Virtuoso, Design Compiler, Integrator; FPGA prototyping, STA, DFT.
Synopsys PrimeTime, Cadence Virtuoso, Design Compiler, Integrator, SystemVerilog, SVA, Python, Perl, Verilog, FPGA
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Electrical Design Engineer
Palo Alto, California, United States
$130k-$179k/yr HybridFull Time
7+ YOEBS/MS in Electrical Engineering; 7+ years PCB design experience; strong analog/digital/power circuitry; EMI/SI knowledge; lab test experience; good communication.
PSpice, LTSpice, Hyperlynx, Oscilloscopes, Logic analyzers, PCB design tools, PCB layout constraints
3mo
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Senior Hardware Design Engineer - PCB design
Warren or Sunnyvale
$158k-$185k/yr HybridFull Time
5+ YOEBachelor's degree in engineering; 5+ years PCB layout design; experience with digital/analog HW interfaces, ESAD tools (Mentor) and high-speed layouts; collaboration across teams.
Mentor Graphics
1w
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Senior Design Engineer
Mountain View or Redmond
$120k-$235k/yr HybridFull Time
1+ YOEAdvanced degree or equivalent experience in EE/CE/CS with substantial digital/SoC design experience; RTL coding in Verilog/SystemVerilog, CDC/Lint closure, synthesis, timing, PPA trade-offs, and post-silicon debug experience.
Verilog, System Verilog, Clock Domain Crossing (CDC)
1mo
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Electronics Design Engineer
Mountain View, California, United States
$140k-$170k/yr OnsiteFull Time
3+ YOEPCBA digital/analog design, communication bus design and debug (CAN, Ethernet, RS-485, USB, SPI, I2C), analog sensor and signal conditioning design, board bring-up and validation; MS/PhD and 3–5 years experience preferred, Altium/ECAD experience.
Altium, ECAD, CAN, Ethernet, RS-485, USB, SPI, I2C, DDR, eMMC
3w
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Senior Logic Design Engineer
Sunnyvale, California, United States
$170k-$250k/yr OnsiteFull Time
10+ YOEBachelor's in Electrical/Computer Engineering, 10+ years front-end digital SoC experience, Verilog/SystemVerilog and synthesis expertise, embedded/mixed-mode design and strong debugging and communication skills.
Verilog, SystemVerilog
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