138 uvm jobs at 35 companies in Lago Vista, TX
2d
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Trimmer/Climber- UVM (Texas)
Austin, Texas, United States
$21-$25/hr FieldFull Time
0+ YOEOutdoor tree-trimming role requiring climbing, lifting, safety awareness, and teamwork. CPR and First Aid required within 90 days; driver's license preferred. Experience ranges from entry level to 12+ months by level.
Personal Protective Equipment (PPE), chainsaws, chippers, hand tools, ropes, saddles, life-support equipment, climbing gear
1mo
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SoC Verification Engineer
Austin or Santa Clara or Hillsboro
$142k-$200k/yr HybridFull Time
3+ YOE3+ years SoC design verification experience (4+ with bachelor's) with OVM/UVM, AMBA protocols, UVM testbench creation, debugging, and test planning; bachelor's or master's in EE/CE/CS or related.
OVM, UVM, CHI, AXI, AHB, APB, VIP, emulation models, system simulation tools
2mo
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Principal Digital Verification Engineer
Austin, Texas, United States
OnsiteFull Time
8+ YOEMasters in Electrical/Computer Engineering with 8+ years or Bachelor's with 10+ years experience; experience in DDR5/DDR6 verification and UVM.
UVM, SystemVerilog, DDR5/DDR6, verification environments, testbench
3mo
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Satellite Design Verification Engineer, Amazon Leo
Austin or Sunnyvale or Redmond or San Diego
$136k-$184k/yr OnsiteFull Time
5+ YOE2+ years UVM, C, SystemC, and scripting; 5+ years verification for communication systems; Bachelor's degree in Electrical Engineering.
UVM, C, SystemC, DPI-C, SystemVerilog, Matlab
3mo
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Principal Design Verification Engineer (Silicon Engineering)
Irvine or Austin or Redmond or Sunnyvale
$210k-$300k/yr OnsiteFull Time
10+ YOEBachelor in ECE/CS and 10+ years in design verification; strong UVM/OVM/VMM, Python, and RTL/ASIC/FPGA experience.
UVM, OVM, VMM, Python, RTL, ASIC, FPGA, constrained random verification
3mo
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Staff Design Verification Engineer – Coherent Interconnect
Boston or Austin
OnsiteFull Time
7+ YOELead verification for cache-coherent interconnect; 7+ years ASIC/SoC verification; SystemVerilog/UVM expertise; strong debugging and collaboration skills.
SystemVerilog, UVM, Verilog, Python
2mo
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CPU Verification Fellow, RISC-V High-Performance Processor
Santa Clara or Austin
$100k-$500k/yr HybridFull Time
Experience leading verification for high-performance CPUs; strong SystemVerilog/UVM; knowledge of RISC-V; ability to guide large engineering teams.
SystemVerilog, UVM, Constrained-Random Verification, Formal Verification, ISA, Debug Methodologies
1mo
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DV Engineer - AI
Austin, Texas, United States
$60k-$135k/yr OnsiteFull Time
5+ YOE5+ years VLSI/HVL verification experience with SV/UVM, AMBA knowledge, testplan and coverage experience, debug skills, and AI/LLM familiarity.
SV, UVM, AMBA, System Verilog, UPF, CPF, RTL, DFT, HVL, LLMs
3mo
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Staff Engineer, GPU Design Verification (Subsystems)
Austin or San Jose
$151k-$252k/yr OnsiteFull Time
6+ YOE6+ years in GPU/CPU/semiconductor design verification; strong SystemVerilog/UVM, C/C++, Python; testbench development; debugging and collaboration skills.
SystemVerilog, UVM, C++, Python, Perl
1mo
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Design Verification Engineer – Physical AI Compute
Santa Clara or Austin or Boston
$75k-$275k/yr OnsiteFull Time
Experience verifying complex digital/SoC systems with SystemVerilog/UVM, C/C++, assertions, formal, emulation and debugging across HW/SW boundaries.
SystemVerilog, UVM, C, C++, formal verification, emulation, FPGA
3mo
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Principal Design Engineer
Austin, Texas, United States
OnsiteFull Time
Design verification expert with SV-UVM, subsystem/SOC verification, ARM-based designs, AMBA protocols, C test development, mentoring, Cadence tools a plus.
SV-UVM, ARM, AMBA, C, Cadence tools
2mo
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Staff Systems Engineer (Austin, TX, US)
Austin, Texas, United States
$114k-$220k/yr OnsiteFull Time
6+ YOEMSEE 6+ years or BSEE 8+ years with systems design; MATLAB; SystemVerilog, UVM, RNM; FPGA/ASIC design; lab equipment; RF/PLL knowledge.
MATLAB, SystemVerilog, UVM, RNM, FPGA, ASIC
2d
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Senior ASIC Verification Engineer - HSIO
Westford or Austin
$136k-$265k/yr OnsiteFull Time
5+ YOEBachelor's or master's degree or equivalent experience, 5+ years relevant experience, and expertise in SystemVerilog, UVM, IP/interconnect protocol verification, coverage, assertions, debugging, and collaboration.
SystemVerilog, UVM, Perl, Python, AI-enabled code assist, root-cause analysis tools
1w
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Digital Design
Austin, Texas, United States
$119k/yr OnsiteFull Time
Master’s degree in electrical, electronics, or computer engineering; knowledge of Python, C/C++, Verilog, SystemVerilog, UVM, functional verification, computer architecture, RTL design, and digital systems.
Python, C, C++, Verilog, SystemVerilog, UVM, Synopsis Design Vision, RTL, Lint, LEC, CDC, STA, RDC
1w
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Design Verification Engineer
Santa Clara or Folsom or Austin
$153k-$229k/yr HybridFull Time
8+ YOEAdvanced SystemVerilog, UVM, C/C++, Python or Perl, and formal verification experience; bachelor's plus 8 years or master's plus 6 years in a related discipline preferred.
SystemVerilog, UVM, C, C++, Python, Perl, DFI, DDR5, LPDDR5, LPDDR6, DIMM, RTL, BIOS, GLS, NLP, XPROP, VIP, BFM
6d
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ASIC Digital Verification Design, Sr Staff Engineer
Austin, Texas, United States
$138k-$208k/yr OnsiteFull Time
8+ YOEBSEE and 8–10+ years of ASIC or SoC verification experience; expertise in SystemVerilog and UVM; protocol knowledge in PCIe, CXL, DDR, or Ethernet; simulator experience and strong debugging skills.
SystemVerilog, UVM, VCS, ModelSim, RTL, PCIe, CXL, DDR, Ethernet
2mo
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Design Verification Engineer (Einfochips)
Austin or San Jose
OnsiteFull Time
6+ YOE6+ years in System Verilog HVL and C/C++, 6+ years in UVM; strong testbench development, debug, and verification closure; experience with DSP, scripting, and version control tools.
SystemVerilog, HVL, C, C++, UVM, SVTB, Make, Perl, Python, Bugzilla, Subversion
6d
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Senior Engineer - Frontend CAD (788102)
Bangalore or Austin or Stockholm or Lund
OnsiteFull Time
10+ YOEBS/MS in electrical engineering, computer science, or related field; 10+ years of ASIC verification experience; SystemVerilog, UVM, scripting, EDA tools, CI, and distributed-team collaboration.
SystemVerilog, UVM, Python, Perl, Bash, C shell (csh), SVA, Verilog, Jenkins, AI/ML
2d
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Senior ASIC Verification Engineer - HSIO
Westford or Austin
$136k-$265k/yr OnsiteFull Time
5+ YOEBachelor's or master's degree or equivalent experience, 5+ years relevant experience, SystemVerilog and UVM expertise, IP or interconnect protocol verification, debugging, analysis, problem solving, and collaboration skills.
SystemVerilog, UVM, Perl, Python
1mo
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Senior Silicon Engineer
Redmond or Mountain View or Santa Clara or Austin or Raleigh or Hillsboro or Boise
$120k-$235k/yr HybridFull Time
5+ YOEExperience verifying silicon using UVM/C, strong RTL and SoC verification background, proficiency with Verilog/System Verilog, and relevant EE/CS/CE degree or equivalent experience.
UVM, C, Verilog, System Verilog, Microsoft Excel