2mo
Save
Mark Applied
Hide
Senior CPU Design Verification Engineer
Austin or Phoenix
$142k-$200k/yr HybridFull Time
4+ YOE4+ years in design verification; SystemVerilog/UVM; pre-silicon CPU/SoC verification; strong debugging; Bachelor's or Master in Electrical or Computer Engineering.
SystemVerilog, UVM, EDA tools, Python, Linux
2mo
Save
Mark Applied
Hide
Senior Technical Staff Engineer - Verification
Chandler, Arizona, United States
OnsiteFull Time
15+ YOESenior verification engineer with 15+ years in functional verification; expert in SystemVerilog, UVM, and formal verification for IP/SoC; strong debugging and cross-functional collaboration.
SystemVerilog, UVM, Formal Verification, IP-level verification, SoC verification, ARM/RISC architectures
1w
Save
Mark Applied
Hide
Director, Digital Design & Verification
Chandler, Arizona, United States
OnsiteFull Time
Proven leader in digital IC design and verification for mixed-signal SoCs with expertise in RTL, verification methodologies (UVM, formal, AMS/DMS), architecture, and team building.
SystemVerilog, UVM, Formal, AMS/DMS, RTL, STA, DFT
1w
Save
Mark Applied
Hide
Senior Engineer I- Design
Chandler, Arizona, United States
OnsiteFull Time
5+ YOEBSEE with 5+ years experience, proficiency in Verilog/SystemVerilog and UVM, Python and TCL scripting, familiarity with Synopsys/Cadence/Siemens EDA tools, and experience with RTL design and verification.
Verilog, SystemVerilog, UVM, Python, TCL, Shell, Synopsys, Cadence, Siemens, AI/ML
2mo
Save
Mark Applied
Hide
Principal Engineer - Digital Design
Chandler, Arizona, United States
OnsiteFull Time
10+ YOEBachelors with 10+ years in digital design; RTL coding/verification; USB/Ethernet PHY knowledge; Verilog/SystemVerilog; UVM/VMM a plus; ASIC flow; CAD tools; timing; scripting.
Verilog, SystemVerilog, UVM, Questa, Design Compiler, Formality, Spyglass, Crossing Clock domain checking, lint, stuck-at, At-Speed scan, Scripting (C, TCL, Perl, Awk, UNIX shell), CVS, Perforce, DesignSync
1w
Save
Mark Applied
Hide
Senior Technical Staff Engineer - Verification
Bangalore or Chandler
OnsiteFull Time
15+ YOE15+ years functional verification experience; expertise in SystemVerilog, UVM, formal methods, RTL and SoC verification; BS/MS in EE/CE or related; strong communication, mentoring, and problem-solving skills.
SystemVerilog, UVM, Formal, RTL, AI/ML
1mo
Save
Mark Applied
Hide
IP Design Verification Engineer
Phoenix or Chandler or Hillsboro or Folsom or Santa Clara
$142k-$200k/yr OnsiteFull Time
3+ YOEDegree in EE/CE (or related) with relevant years of experience; 3+ years in SystemVerilog/Verilog and UVM/OVM; experience with Synopsys VCS, Cadence Xcelium/JasperGold, or Mentor Questa; analog behavioral modeling and PCIe/UCIe experience.
System Verilog, Verilog, UVM, OVM, Synopsys VCS, Cadence Xcelium, JasperGold, Mentor Questa, PCIe, UCIe
1mo
Save
Mark Applied
Hide
Staff Design Verification Engineer (AI/ML)
Chandler, Arizona, United States
OnsiteFull Time
5+ YOEMS EE/CE with 7+ years or PhD with 5+ years (BSEE/BSCE considered); strong SystemVerilog/UVM and Python skills; experience delivering verification to tape-out; knowledge of formal verification and CDC; familiarity with Xcelium and JasperGold.
SystemVerilog, UVM, Python, Xcelium, JasperGold, Verilog-AMS, SDF
2mo
Save
Mark Applied
Hide
Staff Engineer, Design Verification Engineering
Chandler, Arizona, United States
$172k-$199k/yr HybridFull Time
4+ YOEMaster's degree in Electrical Engineering, Materials Engineering, or Physics with 4 years in design verification; or Bachelor's with 6 years; strong SystemVerilog/UVM skills; Verilog-RTL, mixed-signal verification; Xcelium/VCS; scripting (Perl/Python/C).
SystemVerilog, UVM, Verilog-AMS, Cadence AMS, Xcelium, VCS, Perl, Python, C
1mo
Save
Mark Applied
Hide
Senior Design Verification Engineer (eInfochips Inc)
Minneapolis or Phoenix
OnsiteFull Time
Bachelor’s or Master’s in EE/CE or related; strong SystemVerilog and UVM skills; scripting with Python/Perl/Tcl; experience with Cadence Xcelium, Synopsys VCS or Siemens Questa; knowledge of constrained-random verification, SVA, functional coverage and AMBA protocols.
UVM, SystemVerilog, Python, Perl, Tcl, Cadence Xcelium, Synopsys VCS, Siemens Questa, Cadence Palladium, C, SVA, UPF, CPF, Real Number Models (RNM), AMBA (AXI/AHB/APB)
1mo
Save
Mark Applied
Hide
Senior Design Verification Engineer
Tempe or Independence or Arizona or Ohio or San Jose or New York City
$142k-$224k/yr HybridFull Time
8+ YOE8+ years design verification experience with UVM and testbench development; Bachelor's in EE/CE or related; experience with Questa/Xcelium/VCS; AI/agentic DV experience preferred; US citizenship and ability to obtain Secret clearance; travel up to 10%.
UVM, SystemVerilog, VHDL, Verilog, Questa, Xcelium, VCS, Jira
2mo
Save
Mark Applied
Hide
Advanced ASIC FPGA Verification Engineer for Crypto and Cross Domain Solutions
Scottsdale, Arizona, United States
$135k-$150k/yr OnsiteFull Time
5+ YOEBachelor's in Electrical/Computer Engineering plus 5+ years (or Master's with 3+ years); DoD Secret clearance; U.S. citizenship.
SystemVerilog, VHDL, UVM, QuestaSim, ModelSim, Vivado, Jenkins, GitLab CI, Python, Tcl, Bash, Perl
3d
Save
Mark Applied
Hide
FPGA Digital Engineer - 2
Chandler, Arizona, United States
$87k-$131k/yr OnsiteFull Time
2+ YOEBachelor's in EE/CE plus 2 years (or Master's), ability to obtain DoD Secret clearance, FPGA (VHDL/Verilog) experience, Vivado and simulation tool familiarity, and digital interface verification experience.
VHDL, Verilog, AMD Xilinx FPGAs, Vivado IDE, Questa, ModelSim, Vitis Unified IDE, C, C++, OSVVM, UVM
3d
Save
Mark Applied
Hide
Principal FPGA Digital Engineer - 3
Chandler, Arizona, United States
$108k-$162k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE (or MS/PhD) with relevant FPGA/SoC design experience, expertise in VHDL/Verilog and Xilinx toolflow, static timing analysis, bus interfaces, simulation/verification, and ability to obtain DoD Secret clearance.
VHDL, Verilog, AMD Xilinx FPGAs, Vivado IDE, Vitis Unified IDE, Questa/ModelSim, OSVVM, UVM, AXI4, Ethernet, PCIe, UART, SDLC, DDR3, DDR4, DDR5, logic analyzer, oscilloscope, C, C++
2w
Save
Mark Applied
Hide
Staff Digital Design Engineer
Chandler, Arizona, United States
HybridFull Time
11+ YOE>10 years digital design experience, degree in EE/CE/CS or related, fluent Verilog/SystemVerilog, ASIC methodology knowledge, Lint/CDC/RDC experience, RTL and gate-level debug, English proficiency, travel readiness.
Verilog, SystemVerilog, Lint, CDC, RDC, UPF, UVM, AMBA, I2C, STA
3w
Save
Mark Applied
Hide
Senior Digital Engineer
Chandler, Arizona, United States
OnsiteFull Time
5+ YOE5+ years digital design experience, degree in electrical/computer discipline, fluent Verilog/SystemVerilog, ASIC methodology, lint/CDC/RDC experience, RTL and gate-level debug, English proficiency, willing to travel.
Verilog, SystemVerilog, Lint, CDC, RDC, UPF, UVM, AMBA, I2C, STA
1mo
Save
Mark Applied
Hide
Advanced ASIC FPGA Engineer- (Sign-on Bonus Available)
Scottsdale, Arizona, United States
$123k-$136k/yr HybridFull Time
5+ YOEBachelor's in ECE or related STEM plus 5+ years experience (or Master's +3). Must be U.S. citizen and able to obtain Top Secret/SCI clearance. Proficient in VHDL/Verilog/SystemVerilog, ASIC/FPGA tool flow, scripting (Tcl/Python/Perl), and technical communication.
VHDL, Verilog, SystemVerilog, SVA, OVM, UVM, QuestaSim, Questa CDC, ISE, Vivado, Libero, Precision, Synplify, Tcl, Python, Perl, Xilinx, Microchip, Oscilloscope, Logic Analyzer, ChipScope, Microsoft Office
1mo
Save
Mark Applied
Hide
Analog Mixed Signal Modeling Engineer (UL - 02)
Austin or Chandler or Greensboro
HybridFull Time
Master's in EE/Computer Eng required. Experience in mixed-signal product development, analog IC design, SystemVerilog RNM, AMS simulators, verification methodologies, and strong analytical and communication skills.
SystemVerilog Real Number Modeling (SV-RNM), Verilog AMS, AMS simulators, System Verilog Assertions, PSL Assertions, Perforce, GIT, UVM, Simulink, Simscape, Python
3w
Save
Mark Applied
Hide
Applications Engineer - FPGA Prototyping
San Diego or Austin or Boulder or Costa Mesa or Pasadena or Tempe or Wilsonville or Fremont
$167k-$334k/yr HybridFull Time
5+ YOE5+ years in design/verification/FPGA/ASIC or similar; BS/MS in EE/CE/CS; active experience with SystemVerilog/Verilog/VHDL, FPGA tools, scripting, simulation and customer-facing technical support.
SystemVerilog, Verilog, VHDL, SystemC, C/C++, Perl, Python, XML, JSON, proFPGA, HAPS, Xilinx Vivado, Altera Quartus, Questa, Incisive, VCS, OVM, UVM
Explore Jobs
Expand Your Job Search
Top Cities Near Phoenix for Uvm
- Uvm jobs in Mesa, AZ
- Uvm jobs in Chandler, AZ
- Uvm jobs in Gilbert, AZ
- Uvm jobs in Glendale, AZ
- Uvm jobs in Scottsdale, AZ
- Uvm jobs in Peoria, AZ
- Uvm jobs in Tempe, AZ
- Uvm jobs in Surprise, AZ
- Uvm jobs in Avondale, AZ
- Uvm jobs in Goodyear, AZ
- Uvm jobs in Casa Grande, AZ
- Uvm jobs in Buckeye, AZ
- Uvm jobs in Maricopa, AZ
- Uvm jobs in Apache Junction, AZ
- Uvm jobs in Queen Creek, AZ
- Uvm jobs in El Mirage, AZ
- Uvm jobs in Florence, AZ
- Uvm jobs in Fountain Hills, AZ
- Uvm jobs in Paradise Valley, AZ
- Uvm jobs in Coolidge, AZ