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973 verification engineer jobs at 235 companies in California

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Verification Engineer
San Jose or San Diego or Austin or Longmont
$124k-$213k/yr HybridFull Time
AMD
AMDNASDAQ: AMD: Designs and manufactures computer processors and graphics technology.
Experience in IP/ASIC/FPGA verification using UVM, Verilog/SystemVerilog, scripting (Python/Perl), and developing test plans and regression suites; bachelor’s or master’s in computer or electrical engineering.
UVM, Verilog, System Verilog, Python, Perl, PCIe, CXL, NVMe, Ethernet, HLS
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2mo
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Verification Engineer
San Jose or Fort Collins
$120k-$192k/yr OnsiteFull Time
Broadcom
BroadcomNASDAQ: AVGO: Designs and sells semiconductors and infrastructure software to enterprises.
8+ YOEBS in Electrical/Electronic Eng or CS; 8+ years ASIC/RTL verification; SystemVerilog/UVM/OVM; Python/C++; block- and system-level verification; strong debugging and collaboration.
SystemVerilog, UVM, OVM, Python, C/C++, RTL
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1mo
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Verification Engineer
San Jose, California, United States
OnsiteFull Time
Lumilens
Lumilens: Designs photonic interconnects for AI supercomputing infrastructure.
3+ YOEBS/MS in ECE (or equivalent), 3+ years ASIC/SoC functional verification, strong UVM/SystemVerilog skills, testbench development, scripting in Python/Perl/TCL, and familiarity with regression/CI and hardware-assisted verification.
UVM, SystemVerilog, Python, Perl, TCL, Verilog-AMS, Palladium, Veloce, HAPS, Protium, UPF, UCIe, PCIe, CXL, Ethernet, UALink, VIP
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3mo
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Principal Verification Engineer
Austin or Santa Clara
OnsiteFull Time
SiFive
SiFive: Designs and licenses high-performance RISC-V processor intellectual property.
12+ YOE+12 years of experience; BS or MS in Computer Science, Electrical Engineering, or related field; experience with microarchitecture, CPU design, verification flow; strong analytical and troubleshooting skills; ability to collaborate across teams.
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3mo
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ASIC verification engineer
Roseville, California, United States
$120k-$243k/yr OnsiteFull Time
Hewlett Packard Enterprise
Hewlett Packard EnterpriseNYSE: HPE: Provides global edge-to-cloud technology solutions and IT infrastructure services.
6+ YOEBachelor's or Master's in Electrical/Computer Engineering; 6-10 years VLSI design/verification; Verilog/SystemVerilog/UVM; scripting (Python/Perl/TCL); C/C++; EDA/verification tools.
Verilog, SystemVerilog, UVM, Specman, Python, Perl, TCL, C, C++, EDA tools
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3mo
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ASIC verification engineer
Roseville, California, United States
$120k-$243k/yr OnsiteFull Time
Hewlett Packard Enterprise
Hewlett Packard EnterpriseNYSE: HPE: Provides edge-to-cloud IT infrastructure and platform services.
6+ YOE Bachelor's or Master in Electrical or Computer Engineering; 6-10 years in VLSI design/verification; scripting and programming experience; strong VLSI knowledge.
Python, Perl, TCL, C, C++, Verilog, SystemVerilog, UVM, Specman
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1w
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Senior Verification Engineer
Mountain View, California, United States
$120k-$235k/yr HybridFull Time
Microsoft
MicrosoftNASDAQ: MSFT: Develops software, services, devices, and cloud computing solutions.
5+ YOEAdvanced degree or equivalent experience in EE/CE/CS with multi-year design verification experience; ability to pass cloud background and export-control screenings.
Universal Verification Methodology (UVM), Verilog, Zsh, Bash, Python, Perl, Advanced Microcontroller Bus Architecture (AMBA), AXI-4
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Design Verification Engineer
Mountain View, California, United States
$120k-$475k/yr HybridFull Time
MatX
MatX: Designing specialized AI chips for large language model workloads.
Concept-to-silicon verification experience; SystemVerilog, Python, C/C++, Bluespec; UVM and assertion-based verification; formal/simulated verification; portable test creation and silicon debug experience.
SystemVerilog, Python, C/C++, Bluespec, UVM, assertion-based verification (ABV)
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Design Verification Engineer
Mountain View, California, United States
$120k-$475k/yr HybridFull Time
MatX
MatX: Developing custom silicon chips optimized for large language models.
Concept-to-silicon verification experience with SystemVerilog, UVM, ABV, and scripting; production verification and silicon bring-up experience preferred.
SystemVerilog, Python, C/C++, Bluespec, UVM, assertion-based verification (ABV)
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2w
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Senior Verification Engineer
Santa Clara, California, United States
$168k-$311k/yr HybridFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs GPU-accelerated computing and artificial intelligence hardware.
10+ YOE10+ years verification experience, BS/MS in EE/CE/CS or equivalent, expertise in UVM/SystemVerilog/Verilog, Python and C/C++, experience with EDA tools and display protocols, strong debugging and communication skills.
UVM, SystemVerilog, Verilog, Python, C/C++, VCS, Verdi/Debussy, GDB, HLS
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2w
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Senior Verification Engineer
Santa Clara, California, United States
$168k-$311k/yr HybridFull Time
NVIDIA
NVIDIANASDAQ: NVDA: Designs graphics processing units and artificial intelligence hardware.
10+ YOE10+ years verification experience, strong UVM/SystemVerilog/Verilog/Python/C/C++ skills, experience with constrained-random stimulus, coverage, assertions, and EDA tools; BS/MS in EE/CE/CS or equivalent experience.
UVM, SystemVerilog, Verilog, Python, C/C++, VCS, Verdi, Debussy, GDB, HLS
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3mo
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ASIC verification engineer
Roseville, California, United States
$120k-$243k/yr OnsiteFull Time
Hewlett Packard Enterprise
Hewlett Packard EnterpriseNYSE: HPE: Providing global edge-to-cloud infrastructure and IT solutions for businesses.
6+ YOE6-10 years in VLSI design/verification; BS/MS in Electrical or Computer Engineering; scripting (Python/Perl/TCL); programming (C/C++); Verilog/SystemVerilog; UVM; knowledge of EDA tools.
Verilog, SystemVerilog, UVM, Python, Perl, TCL, C, C++
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2mo
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Physical Verification Engineer
Phoenix or Santa Clara or Hillsboro
$129k-$245k/yr HybridFull Time
Intel
IntelNasdaq: INTC: Designs and manufactures microprocessors and semiconductor components.
3+ YOEUS citizenship, ability to obtain US government security clearance, Bachelor in Electrical/Computer Engineering or STEM, 3+ years in CMOS processes and layout verification, 3+ years in parasitic extraction and scripting
Python, Perl, Tcl, Shell, StarRC, Quantus, xACT, ICV, Calibre, Pegasus, LVS, DRC, ERC, PERC, Parasitic Extraction Tools
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Design Verification Engineer
Santa Clara, California, United States
$45k-$121k/yr OnsiteFull Time
Wipro
WiproNYSE: WIT: Global technology services and consulting for digital transformation.
3+ YOERequires 3–5 years of experience with VLSI hardware verification, SystemVerilog, UVM, AMBA protocols, test planning, coverage analysis, simulation debugging, regressions, and power-aware verification.
SystemVerilog, UVM, AMBA, UPF, CPF, VLSI, HVL
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1mo
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Design Verification Engineer
San Francisco, California, United States
OnsiteFull Time
Apple
AppleNASDAQ: AAPL: Designs and sells consumer electronics, software, and online services.
Digital-focused design verification for pre-silicon IP: DV methodology, test-plan and verification environment development, test writing, debug, coverage, and RTL sign-off for tape-out.
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2w
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Design Verification Engineer
Aliso Viejo or San Jose or Córdoba or Toronto
OnsiteFull Time
indie Semiconductor
indie SemiconductorNASDAQ: INDI: Develops next-generation semiconductors and software for automotive sensing and connectivity.
3+ YOEBachelors in EE/CE/CS,3+ years verification experience, SystemVerilog/UVM, coverage-driven verification, C/C++ and scripting (Python,Tcl,Perl),test planning and debug skills.
SystemVerilog, UVM, C, C++, Python, Tcl, Perl
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1mo
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Formal Verification Engineer
San Jose, California, United States
$150k-$350k/yr OnsiteFull Time
Alpha Design AI
Alpha Design AI: AI-native EDA platform for semiconductor design and verification.
Deep formal verification expertise, experience with assertion-based verification and proof debugging, proficiency scripting in Python or Tcl, and hands-on use of formal EDA tools to verify RTL and production IP.
JasperGold, VC Formal, Questa Formal, SystemVerilog Assertions (SVA), Python, Tcl
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1mo
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ASICS Design Verification Engineer
San Diego, California, United States
$116k-$173k/yr OnsiteFull Time
Qualcomm
QualcommNASDAQ: QCOM: Designs and manufactures semiconductors and wireless telecommunications products.
2+ YOEBachelor's in engineering or science and 2+ years ASIC design/verification experience (Master's/PhD alternatives available). Experience with SystemVerilog/UVM, testbench development, coverage, assertions, UPF, formal verification, and scripting (Perl/Python).
SystemVerilog-UVM, SystemVerilog, Verilog, VHDL, C, C++, Perl, Python, UVM, OVM, Unified Power Format (UPF), AMBA, AXI, AHB, APB
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2mo
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ASIC Verification Engineer
San Jose, California, United States
OnsiteFull Time
Axiado
Axiado: Creates AI-driven security processors for data center infrastructure.
8+ YOE8+ years in UVM verification; RTL/gate-level verification; test plan and testbench development in C/Assembly/SystemVerilog; AMBA AXI/AHB/APB; PCIe/USB/Ethernet; scripting; repository and bug-tracking tools.
UVM, SystemVerilog, C, Assembly, Python, Shell, Perl, AMBA AXI, AHB, APB, PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART, Git, JIRA, Bitbucket, Jenkins
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Verification CAD Engineer
Milpitas, California, United States
$160k-$265k/yr HybridFull Time
Sandisk
SandiskNasdaq: SNDK: Designs and manufactures flash memory and data storage products.
7+ YOEB.S./M.S. in EE/CE/CS,7+ years design verification experience,expert SystemVerilog/UVM and SVA/CDV,advanced Python and Shell skills,Linux and regression farm experience (LSF/NC/Slurm),familiarity with Cadence verification tools.
SystemVerilog, UVM, SVA, Python, Shell, Perl, Xcelium, SimVision, vManager, Verissium, Linux, LSF, NC, Slurm
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