2mo
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ASIC verification engineer
Roseville, California, United States
$120k-$243k/yr OnsiteFull Time
6+ YOEBachelor's or Master's in Electrical/Computer Engineering; 6-10 years VLSI design/verification; Verilog/SystemVerilog/UVM; scripting (Python/Perl/TCL); C/C++; EDA/verification tools.
Verilog, SystemVerilog, UVM, Specman, Python, Perl, TCL, C, C++, EDA tools
2mo
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ASIC verification engineer
Roseville, California, United States
$120k-$243k/yr OnsiteFull Time
6+ YOE Bachelor's or Master in Electrical or Computer Engineering; 6-10 years in VLSI design/verification; scripting and programming experience; strong VLSI knowledge.
Python, Perl, TCL, C, C++, Verilog, SystemVerilog, UVM, Specman
2mo
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ASIC verification engineer
Roseville, California, United States
$120k-$243k/yr OnsiteFull Time
6+ YOE6-10 years in VLSI design/verification; BS/MS in Electrical or Computer Engineering; scripting (Python/Perl/TCL); programming (C/C++); Verilog/SystemVerilog; UVM; knowledge of EDA tools.
Verilog, SystemVerilog, UVM, Python, Perl, TCL, C, C++
2mo
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SMTS Design Verification Engineer
Minneapolis or Boise or Folsom or Richardson or San Jose
$178k-$389k/yr OnsiteFull Time
6+ YOEBS/MS/PhD in EE/CE or related; 6+ years UVM/SystemVerilog functional verification; experience building UVM testbenches, coverage-driven methodology, protocol/interface verification, RTL/testbench debug, and post-silicon bring-up support.
UVM, SystemVerilog, SystemVerilog Assertions (SVA), JasperGold, VC Formal, Verilog-AMS, Real-number modeling (RNM), ATE
2mo
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Staff Engineer - ASIC Verification
San Jose or Folsom
$145k-$286k/yr OnsiteFull Time
6+ YOEBS in electrical engineering or computer science; 6-8 years verification; RTL debugging, scoreboarding, and code coverage; test plans and coverage definitions.
SystemVerilog, UVM, C, DDR, PCIe/NVMe, NAND
1w
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IP Design Verification Engineer
Folsom, California, United States
$106k-$149k/yr HybridFull Time
3+ YOEExperience with Verilog/VHDL/SystemVerilog, C/C++/Python, FPGA/emulation, hardware/software debug, computer architecture knowledge; Bachelor's+3yrs or Master's+1yr in electronics/computer engineering.
Verilog, VHDL, SystemVerilog, C, C++, Python, FPGA, VCS, Verdi, DVE, OVM/UVM, logic analyzers, oscilloscopes, protocol analyzers, IA-Core Assembly
3w
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Digital Verification Engineer - Weapon Subsystems 2
Albuquerque or Livermore or United States
$122k-$238k/yr HybridFull Time, Temporary
Bachelor's in relevant discipline (or equivalent experience), ability to obtain DOE Q-level clearance, expertise in formal verification, VHDL/Verilog/SVA proficiency, strong analytical and written communication skills.
VHDL, Verilog, SystemVerilog Assertions (SVA)
1mo
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Digital Verification Engineer - Weapon Subsystems 2
Livermore or California or New Mexico or United States
$122k-$238k/yr HybridFull Time, Temporary
Bachelor's degree or equivalent, ability to obtain DOE Q-level (Top Secret) clearance, several years applying formal verification to FPGA/ASIC, proficiency with VHDL, Verilog, and SystemVerilog Assertions (SVA), strong analytical and written communication skills.
VHDL, Verilog, SystemVerilog Assertions (SVA)
4w
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Test Engineer
Byron, California, United States
$118k-$190k/yr OnsiteFull Time
2+ YOEBachelor's in engineering, 2+ years test experience in hardware verification or lab testing, hands-on with propulsion/battery/EV systems, DAQ (National Instruments, Dewesoft), proficiency with Python, MATLAB, or LabVIEW, and strong troubleshooting and reporting skills.
National Instruments, Dewesoft, Python, MATLAB, LabVIEW, CAD, DAQ, HIL
2mo
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Principal Systems Design Engineer
Folsom, California, United States
$175k-$300k/yr OnsiteFull Time
10+ YOEBachelor's in electrical or computer engineering with 10+ years of experience; strong hardware/software systems design, verification, and leadership skills.
20h
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Principal Engineer, SOC Design
Folsom, California, United States
$199k-$319k/yr OnsiteFull Time
15+ YOEExtensive SoC architecture and RTL development experience with modern DRAM technologies, verification/debugging skills, FPGA prototyping or silicon bring-up experience, and strong technical leadership.
SystemVerilog, Verilog, FPGA
1mo
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Tech Staff Engineer - Firmware
Roseville, California, United States
$88k-$232k/yr OnsiteFull Time
10+ YOEBS/MS in CS/CE or equivalent, 10+ years embedded systems development and verification, strong C/C++/Python, experience with PCIe/NVMe, secure boot/security firmware, leadership and documentation skills.
C, C++, Python, Rust, ARM Architecture, NVMe, PCIe, Caliptra Open-Source Root-of-Trust, Cadence Palladium, Cadence Protium, Bus/Logic Analyzers, PCIe Exercisers, Git, Perforce, JIRA, Linux, Perl, Agile Scrum, DevOps, Secure Development Life Cycle
4w
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IP Logic Design Engineer
Rancho Cordova, California, United States
$105k-$165k/yr OnsiteFull Time
7+ YOEMS in ECE with 7+ years or BS with 9+ years; expertise in Verilog/SystemVerilog and ASIC flow (RTL, synthesis, STA, ECO); experience with lint, CDC/RDC analysis, verification tools, scripting, and pre/post-silicon debug; 3D NAND experience preferred.
SystemVerilog, Verilog, RTL, synthesis, Static Timing Analysis (STA), ECO, lint tools, CDC/RDC analysis, SystemVerilog Assertions (SVAs), Gate-level simulation (GLS), Design for Testability (DFT)
1d
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TRA CAD Technician
Tracy, California, United States
$32-$37/hr OnsiteFull Time
2+ YOEDevelop and revise AutoCAD drawings, maintain Autodesk Vault and engineering documentation, perform field verification, HS diploma required, assoc. degree preferred, ~2 years related experience, must be 18 and English proficient.
AutoCAD, Inventor, Autodesk Vault, Microsoft Office
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