259 verification engineer jobs at 53 companies in Hutto, TX
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Verification Engineer
San Jose or San Diego or Austin or Longmont
$124k-$213k/yr HybridFull Time
Experience in IP/ASIC/FPGA verification using UVM, Verilog/SystemVerilog, scripting (Python/Perl), and developing test plans and regression suites; bachelor’s or master’s in computer or electrical engineering.
UVM, Verilog, System Verilog, Python, Perl, PCIe, CXL, NVMe, Ethernet, HLS
2mo
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Design Verification Engineer
Lakeway or Austin
OnsiteFull Time
7+ YOEBSc/MSc in engineering or CS, 7+ years verification experience, expert SystemVerilog/UVM development, protocol verification (AXI, DDRx, PCIe, USBx), verification planning, and ability to travel; eligible to work in the US.
SystemVerilog, UVM, Specman/e, C, C++, Python, Perl
3mo
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Principal Verification Engineer
Austin or Santa Clara
OnsiteFull Time
12+ YOE+12 years of experience; BS or MS in Computer Science, Electrical Engineering, or related field; experience with microarchitecture, CPU design, verification flow; strong analytical and troubleshooting skills; ability to collaborate across teams.
2mo
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ASIC Verification Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOE5+ years verification experience, 2+ full block/system verification cycles, deep VLSI verification knowledge, experience with SystemVerilog/UVM/eRM, familiarity with data-paths/protocols (Ethernet preferred), mentoring and cross-team collaboration.
SystemVerilog, UVM, eRM, RTL, Ethernet
2mo
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Senior Verification Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOEBSEE+5yrs or MSEE+3yrs or PhD+1yr; expertise in Verilog/SystemVerilog, OVM/UVM, formal methods; knowledge of DDR, PCIe, AMBA; scripting in Python/Perl and UNIX/Linux; strong debugging and verification planning skills.
Verilog, SystemVerilog, VHDL, OVM/UVM, SystemVerilog assertions (SVA), DDR, PCIe, AMBA (CHI, ACE, AXI), AI/LLM, Python, Perl, UNIX/Linux
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ASIC Verification Engineer
Austin, Texas, United States
$116k-$190k/yr HybridFull Time
2+ YOEBS/MS in Electrical/Computer Engineering or equivalent, 2+ years verification experience, SystemVerilog/UVM, Perl or Python scripting, experience with synthesis/simulation and debug tools, strong debugging and collaboration skills.
SystemVerilog, UVM, Perl, Python, dc_shell, VCS, Debussy, GDB
2w
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CPU Verification Engineer
Austin, Texas, United States
$106k-$200k/yr HybridFull Time
3+ YOEDegree in EE/CE or related STEM plus 2–3+ years verification experience; expertise in SystemVerilog/UVM, scripting (Python/Perl), C++, CPU architecture knowledge, debugging and verification methodologies.
SystemVerilog, UVM, Python, Perl, C++, VCS, GIT, Assembly
4w
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Design Verification Engineer
Raleigh or Hillsboro or Austin or Mountain View or Redmond
$102k-$202k/yr HybridFull Time, Contract
1+ YOEMaster's+1 or Bachelor's+2 years technical engineering experience (or equivalent); verification of silicon/IP using UVM/System Verilog/Formal; Python scripting; knowledge of CHI/AMBA/PCIe/CXL preferred; pass Microsoft Cloud Background Check and export-control screening.
UVM, Formal, System Verilog, Python
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Associate Staff Verification Engineer - Wireless
Austin, Texas, United States
$126k-$234k/yr OnsiteFull Time
3+ YOEBachelor's or master's degree in electrical or computer engineering, 3–8 years of experience, and expertise in SV-UVM, C, verification, automation, SystemVerilog assertions, coverage, UPF, and real-number modeling.
UVM, C, MATLAB, Electronic Design Automation (EDA), SystemVerilog, SystemVerilog Assertion, UPF, Real Number Modeling (RNM), SPICE
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Associate Staff Verification Engineer - Wireless
Austin, Texas, United States
$126k-$234k/yr OnsiteFull Time
3+ YOEBachelor's or master's degree in electrical or computer engineering; 3–8 years' experience; SV-UVM, C, scripting, automation, verification, SystemVerilog assertions, coverage, UPF, and real-number modeling skills.
UVM, C, MATLAB, SystemVerilog, SystemVerilog Assertion, UPF, Spice
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Senior Firmware Verification Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOEBS/MS in EE or Computer Engineering required; 5+ years firmware verification experience in pre-silicon; SystemVerilog, C, Python/Perl skills; familiarity with RTL, emulation, and lab test equipment.
SystemVerilog, UVM, C, Python, Perl, RTL, FPGA, QEMU, SimVision, Verdi, oscilloscopes, power supplies, logic analyzers
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ASIC Engineer, Design Verification
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
6+ YOEBachelor's in CS/CE or equivalent; 6+ years SystemVerilog/UVM or C/C++ verification and IP/SoC level verification experience; EDA tools and scripting (Python, TCL, Perl, Shell).
SystemVerilog, UVM, C, C++, Python, TCL, Perl, Shell, Mercurial, Hg, Git, SVN, SV Assertions, Formal, Emulation, PCIe, RoCE, DDR, HBM, Ethernet
2mo
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Design Verification (DV) Engineer
Mountain View or Austin
$200k-$320k/yr OnsiteFull Time
Expert SystemVerilog and UVM verification skills; hands-on experience with logic simulators and waveform debuggers; coverage-driven verification, assertion and regression infrastructure experience; optional formal, Python/Tcl scripting, and RISC-V familiarity.
SystemVerilog, UVM, Synopsys VCS, Cadence Xcelium, Synopsys Verdi, Cadence SimVision, Python, Tcl, LLVM, RISC-V
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Senior ASIC Verification Engineer
Austin or Santa Clara
$136k-$265k/yr HybridFull Time
5+ YOEBachelors/Masters in CS/CE/EE (or equivalent experience), 5+ years experience, SystemVerilog OOP, verification methodology (UVM), VCS/Debussy/GDB exposure, experience with random stimulus, functional coverage, assertions, firmware/hardware verification.
SystemVerilog, VCS, Debussy, GDB, UVM, C, RISC-V Assembly
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IP Verification Engineer
Austin, Texas, United States
HybridFull Time
Several years of industry RTL verification experience, strong SystemVerilog/UVM skills, RTL testbench and TLM modeling, HW emulation experience, scripting (TCL/Python/Perl), familiarity with SerDes/PCIe/ARM/DSP/Ethernet and AMBA protocols, and BS/MS in EE/CE.
SystemVerilog, UVM, TLM, SerDes, PCIe, ARM, DSP, Ethernet, TCL, Python, Perl, C, Assembly, Linux, GIT, LSF, AMBA, APB, AXI, ACE-Lite, CHI
2mo
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Digital Design Verification Engineer
Bristol or Austin
£125k/yr OnsiteFull Time
5+ YOE5+ years in digital verification for high-performance ASICs/SoCs; strong SystemVerilog, SVA, UVM, Cocotb, formal verification, CDC/RDC, and algorithm modelling (MATLAB/Simulink or Python/NumPy) skills; experience with high-speed IP (SerDes, DDR/HBM, PCIe).
SystemVerilog, UVM, SVA, CocoTB, MATLAB/Simulink, Python, NumPy, Jasper, FPGA, RTL simulation, formal verification, linting, CDC/RDC, STA, UPF, CPF, gate-level simulation
2w
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ASIC SoC Verification Engineer (788438)
Austin, Texas, United States
HybridFull Time
Experience in SoC/IP/SubSystem verification, SystemC/TLM and RTL environments, hardware emulation, knowledge of high-speed interfaces, strong problem-solving and communication;BS required, MS preferred.
SystemC/TLM, RTL, hardware emulation
1w
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Security IP Verification Engineer
Austin, Texas, United States
$162k-$219k/yr HybridFull Time
5+ YOEBachelor's or master's degree in computer science or electrical/computer engineering plus 5+ years in IP, subsystem, or SoC design verification; expertise in digital hardware, UVM, SystemVerilog, C, security, and scripting.
UVM, SystemVerilog, Verilog, C, Perl, Python, Tcl, ARM, Assembler, AXI, AHB, Tarmac
2mo
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Design Verification Engineer (Einfochips)
Austin or San Jose
OnsiteFull Time
6+ YOE6+ years in System Verilog HVL and C/C++, 6+ years in UVM; strong testbench development, debug, and verification closure; experience with DSP, scripting, and version control tools.
SystemVerilog, HVL, C, C++, UVM, SVTB, Make, Perl, Python, Bugzilla, Subversion
2mo
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Design Verification Engineer
Austin, Texas, United States
OnsiteFull Time
Verify high-throughput cellular baseband modems and transceiver link controllers; strong problem solving and technical aptitude for complex engineering challenges.
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