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232 verification engineer jobs at 57 companies in Oceanside, CA

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Verification Engineer
San Jose or San Diego or Austin or Longmont
$124k-$213k/yr HybridFull Time
AMD
AMDNASDAQ: AMD: Designs and manufactures computer processors and graphics technology.
Experience in IP/ASIC/FPGA verification using UVM, Verilog/SystemVerilog, scripting (Python/Perl), and developing test plans and regression suites; bachelor’s or master’s in computer or electrical engineering.
UVM, Verilog, System Verilog, Python, Perl, PCIe, CXL, NVMe, Ethernet, HLS
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3mo
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Design Verification Engineer
San Diego, California, United States
OnsiteFull Time
Apple
AppleNASDAQ: AAPL: Designs and sells consumer electronics, software, and online services.
3+ YOEBS degree with 3+ years of experience in digital verification; strong SystemVerilog, scripting (Python/Perl), C/C++; knowledge of verification methodologies (UVM) and digital design fundamentals.
SystemVerilog, Digital simulation, Python, Perl, C, C++
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2w
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ASICS Design Verification Engineer
San Diego, California, United States
$116k-$173k/yr OnsiteFull Time
Qualcomm
QualcommNASDAQ: QCOM: Designs and manufactures semiconductors and wireless telecommunications products.
2+ YOEBachelor's in engineering or science and 2+ years ASIC design/verification experience (Master's/PhD alternatives available). Experience with SystemVerilog/UVM, testbench development, coverage, assertions, UPF, formal verification, and scripting (Perl/Python).
SystemVerilog-UVM, SystemVerilog, Verilog, VHDL, C, C++, Perl, Python, UVM, OVM, Unified Power Format (UPF), AMBA, AXI, AHB, APB
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2mo
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Staff SoC Verification Engineer
San Diego, California, United States
$115k-$170k/yr OnsiteFull Time
Marvell
MarvellNASDAQ: MRVL: Designs and develops high-performance semiconductor and infrastructure solutions.
3+ YOEBS in engineering with 3-5+ years in verification; strong SoC verification, UVM, SystemVerilog, C/C++, DPI; teamwork and problem solving.
UVM, SystemVerilog, C, C++, DPI
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Design Verification Engineer - Viasat Government
Marlborough or Carlsbad
$133k-$210k/yr OnsiteFull Time
Viasat
ViasatNASDAQ: VSAT: Provider of global satellite-based connectivity and secure communication solutions.
5+ YOEBachelor's in Electrical or Computer Engineering; 5+ years hardware verification with SystemVerilog/UVM; RTL verification; strong SystemVerilog/UVM; experience with industry EDA tools; US citizenship and active Secret clearance; willingness to travel up to 10%
SystemVerilog, UVM, Siemens Questa, Cadence, Synopsys, Mentor, Python, TCL
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2w
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Design Verification Engineer
San Diego, California, United States
$81k-$142k/yr OnsiteFull Time
General Atomics
General Atomics: Designs and manufactures unmanned aircraft and nuclear technology systems.
3+ YOEBachelor's in engineering (or equivalent experience); 3+ years engineering experience; strong knowledge of ASME Y14.100 and Y14.5, PDM experience, ability to read/interprete drawings, lead teams, and obtain DoD clearance.
Product Data Management (PDM)
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Principal/ Sr. Principal Digital Verification Engineer
San Diego, California, United States
$125k-$235k/yr OnsiteFull Time
Northrop Grumman
Northrop GrummanNYSE: NOC: Develops and manufactures advanced aerospace, defense, and space systems.
5+ YOEUS citizen able to obtain Secret clearance. Bachelor’s in EE or STEM required. 5+ years digital verification experience (Principal) or 8+ years (Sr. Principal). VHDL, FPGA verification, Siemens Questa, verification planning, and simulation/debug skills.
VHDL, FPGA, Siemens Questa Simulator, OSVVM, Perl, TCL, Bash, Makefile, Linux, Siemens Lint, Siemens Inspect, Siemens CDC
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Principal Design Verification Engineer (Silicon Engineering)
Sunnyvale or Austin or Irvine or Redmond
$210k-$310k/yr OnsiteFull Time
SpaceX
SpaceX: Designs and launches advanced rockets and satellite internet constellations.
10+ YOEBachelor’s in electrical/computer engineering or computer science; 10+ years in design verification and test bench development.
UVM, OVM, VMM, Python, RTL
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FPGA Verification Engineer, Air Vehicles
Costa Mesa, California, United States
$123k-$171k/yr OnsiteFull Time
Anduril Industries
Anduril Industries: Defense technology building autonomous military hardware and software.
2+ YOEBachelor's in EE/CE, 2+ years FPGA/ASIC verification, proficient in SystemVerilog, UVM, SVA, industry simulators, Git, Linux; eligible to obtain U.S. Secret clearance.
SystemVerilog, UVM, SVA, Questa, VCS, Xcelium, Vivado, Git, Linux, Python, Tcl, Makefile, SVUnit, Nix
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Principal/ Sr. Principal Digital Verification Engineer
San Diego, California, United States
$125k-$235k/yr OnsiteFull Time
Northrop Grumman
Northrop GrummanNYSE: NOC: Designs and manufactures advanced aerospace and defense systems.
5+ YOEBachelor's in EE or other STEM; 5+ (Principal) or 8+ (Sr Principal) years digital verification experience; VHDL and FPGA verification; Siemens Questa Simulator; US citizenship and ability to obtain Secret clearance.
VHDL, Siemens Questa Simulator, OSVVM, Perl, TCL, Bash, Makefile, Siemens Lint, Siemens Inspect, Siemens CDC
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2mo
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Satellite Design Verification Engineer, Amazon Leo
Austin or Sunnyvale or Redmond or San Diego
$136k-$184k/yr OnsiteFull Time
Amazon
AmazonNASDAQ: AMZN: Global online retail and cloud computing technology provider.
5+ YOE2+ years UVM, C, SystemC, and scripting; 5+ years verification for communication systems; Bachelor's degree in Electrical Engineering.
UVM, C, SystemC, DPI-C, SystemVerilog, Matlab
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ASIC Design Verification Engineer
Irvine or Andover or Broomfield
$129k-$207k/yr OnsiteFull Time
Broadcom
BroadcomNASDAQ: AVGO: Designs and sells semiconductors and infrastructure software to enterprises.
3+ YOEConstrained-random design verification experience using System Verilog/UVM, coverage-driven methodologies, experience with VCS/Incisive and scripting (Python/Perl). Degree with significant related experience required (varies by degree).
System Verilog, UVM, VCS, Incisive, Python, Perl
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GPU Design Verification Engineer
San Diego, California, United States
$180k-$301k/yr OnsiteFull Time
MediaTek
MediaTekTaiwan Stock Exchange: 2454: Designs and develops system-on-chip solutions for electronic devices.
10+ YOEMS/PhD or equivalent,10+ years ASIC design verification experience,SystemVerilog/UVM,constrained random,functional coverage,hw/sw co-simulation,emulation,strong debugging and GPU architecture knowledge.
SystemVerilog, UVM, emulation
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Senior Software Verification & Validation Engineer
Irvine, California, United States
OnsiteFull Time
Fortive
FortiveNYSE: FTV: Manufactures professional instrumentation, industrial tools, and specialized software.
3+ YOEBachelor's in a technical discipline, 3+ years embedded software V&V or system testing, experience with requirements-based verification, Python scripting, test documentation, and cross-functional collaboration.
Python, JIRA, Azure DevOps, Polarion, Jama, Windows, Microsoft Word, Microsoft Excel, Microsoft PowerPoint, Microsoft Outlook, multimeter, oscilloscope, function generator, logic analyzer
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3mo
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Lead Verification & Validation Engineer
Palo Alto or Irvine
$130k-$155k/yr OnsiteFull Time
ALTEN
ALTENEuronext Paris: ATE: Provides engineering and technology consulting services to industrial clients.
5+ YOELead V&V strategy, mentor engineers, design/test automation, and oversee automotive software/system validation.
CAN, LIN, Ethernet, FlexRay, dSPACE, Vector VT, DBC, LDF, ARXML, HIL, MATLAB, Python, C/C++, Automotive testing tools
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V and V Engineer System Verification Engineer
Irvine, California, United States
$120k-$130k/yr OnsiteFull Time
Tata Consultancy Services
Tata Consultancy ServicesNational Stock Exchange of India: TCS: Global provider of IT services, consulting, and business solutions.
10+ YOE9+ years system/software testing in aerospace with embedded testing, scripting for automation, avionics standards (DO-178b/ARP-4754A), experience with A429/CAN and tools like DOORS, SVN or MKS; Bachelor's in computer science required.
DOORS, SVN, MKS, A429, CAN, DO-178b
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3mo
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ASIC Design Verification Engineer (All Levels)
San Diego, California, United States
$160k-$237k/yr OnsiteFull Time
Marvell Technology
Marvell TechnologyNASDAQ: MRVL: Developing semiconductor solutions for cloud, enterprise, and AI infrastructure.
4+ YOEBS/ MS/ PhD with 2-10+ years verification experience; SystemVerilog/UVM; test planning and coverage; Python/Perl; Linux; C++/ARM; networking knowledge a plus.
SystemVerilog, UVM, Python, Perl, EDA tools, Linux, C++, ARM assembly
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Associate ASIC/FPGA Design or Verification Engineer
El Segundo or Huntington Beach or Fairfax
$99k-$133k/yr OnsiteFull Time
Boeing
BoeingNYSE: BA: Designing and manufacturing commercial aircraft and defense systems.
2+ YOEUS citizenship and ability to obtain U.S. Secret clearance; BS in engineering or related field; experience with ASIC/FPGA design or verification and HDL (Verilog/VHDL/System Verilog); familiarity with verification methodologies and scripting.
Verilog, VHDL, System Verilog, System Verilog Assertions, UVM, Palladium, Make, Perl, Python, svn, cvs, git, Linux, JESD204C, PCIe, Ethernet
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ASIC/FPGA Verification Engineer (Experienced, Lead, or Senior)
El Segundo or Huntington Beach or Fairfax
$120k-$239k/yr OnsiteFull Time
Boeing
BoeingNYSE: BA: Designs and manufactures aircraft, defense systems, and space technology.
5+ YOEBachelor's in engineering or related field, 5+ years ASIC/FPGA verification experience, proficiency in SystemVerilog/UVM, OOP principles, coverage and code-coverage closure, waveform debug, revision control, and Linux.
UVM, SystemVerilog, SystemVerilog Assertions, svn, cvs, git, Linux, Palladium, Make, Perl, Python
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Sr. Principal AMS Verification Engineer (Irvine, CA, US)
Irvine, California, United States
$143k-$286k/yr OnsiteFull Time
Skyworks Solutions
Skyworks SolutionsNASDAQ: SWKS: Designs and manufactures analog and mixed-signal semiconductor solutions.
8+ YOERequires BS+15 yrs (MS+12 or PhD+8) experience; strong AMS design/verification background, Verilog-A and SystemVerilog RNM modeling, Cadence Virtuoso/ADS experience, Python scripting, leadership and communication skills.
Cadence Virtuoso, ADS, Verilog-A, SystemVerilog, SystemVerilog Real Number Modeling (RNM), Python
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