668 verification engineer jobs at 169 companies in Pacheco, CA
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Verification Engineer
San Jose or Fort Collins
$120k-$192k/yr OnsiteFull Time
8+ YOEBS in Electrical/Electronic Eng or CS; 8+ years ASIC/RTL verification; SystemVerilog/UVM/OVM; Python/C++; block- and system-level verification; strong debugging and collaboration.
SystemVerilog, UVM, OVM, Python, C/C++, RTL
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Verification Engineer
San Jose, California, United States
OnsiteFull Time
3+ YOEBS/MS in ECE (or equivalent), 3+ years ASIC/SoC functional verification, strong UVM/SystemVerilog skills, testbench development, scripting in Python/Perl/TCL, and familiarity with regression/CI and hardware-assisted verification.
UVM, SystemVerilog, Python, Perl, TCL, Verilog-AMS, Palladium, Veloce, HAPS, Protium, UPF, UCIe, PCIe, CXL, Ethernet, UALink, VIP
1w
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Principal Verification Engineer
Mountain View or Redmond or Hillsboro or Austin or Raleigh
$143k-$275k/yr HybridFull Time
3+ YOERequires a degree in electrical engineering, computer engineering, computer science, or related field and 3–8+ years of technical engineering experience depending on degree; verification, UVM, RTL, simulation, scripting, and security screening required.
Universal Verification Methodology (UVM), C, Zsh, Bash, Python, Perl, Verilog, Microsoft Azure, AXI, AMBA
2w
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Design Verification Engineer
Santa Clara or Folsom or Austin
$166k-$250k/yr HybridFull Time
6+ YOEExperienced verification engineer with SystemVerilog, UVM, C/C++, Python or Perl, DDR memory verification, formal verification, and cross-functional hardware, firmware, and software collaboration experience.
SystemVerilog, UVM, C, C++, Python, Perl, DDR5, LPDDR5, LPDDR6, DFI, DIMMs, RTL, BIOS, GLS, NLP, XPROP, VIPs, BFMs
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Principal Verification Engineer
Austin or Santa Clara
OnsiteFull Time
12+ YOE+12 years of experience; BS or MS in Computer Science, Electrical Engineering, or related field; experience with microarchitecture, CPU design, verification flow; strong analytical and troubleshooting skills; ability to collaborate across teams.
1d
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CPU Verification Engineer
Austin or Santa Clara
OnsiteFull Time
Requires a BS in electrical or computer engineering or equivalent experience; expertise in CPU verification, C/C++/assembly, Verilog, SystemVerilog, UVM, coverage, assertions, and verification flows.
C, C++, UVM, SystemVerilog, Verilog, Verilog simulator
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Design Verification Engineer
Mountain View, California, United States
$120k-$475k/yr HybridFull Time
Concept-to-silicon verification experience; SystemVerilog, Python, C/C++, Bluespec; UVM and assertion-based verification; formal/simulated verification; portable test creation and silicon debug experience.
SystemVerilog, Python, C/C++, Bluespec, UVM, assertion-based verification (ABV)
6d
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Verification Engineer (CONTRACT)
Santa Clara, California, United States
$60k-$149k/yr OnsiteContract
5+ YOERequires 5–8 years of experience, strong SystemVerilog and UVM knowledge, debugging skills, protocol understanding, and experience developing verification environments, tests, coverage, and regressions.
SystemVerilog, UVM, VLSI, HVL
1d
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Technical Staff Engineer - Verification
Chandler or San Jose or San Jose or Roseville or Austin
$91k-$232k/yr OnsiteFull Time
12+ YOEBS or MS in electrical/electronic engineering and 12+ years verifying complex SoC designs. Requires SystemVerilog, UVM, formal verification, methodology development, automation, scripting, and SoC architecture expertise.
SystemVerilog, UVM, Python, TCL/TK, C, C++, Siemens, Cadence, Synopsys, Git, Perforce, svn, ARM, RISC-V, PCIe, DDR4, DDR5, LPDDR4X, MIPI DSI, MIPI CSI, Ethernet MAC, USB, FPGA, SoC, RTL, GDS
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Senior Verification Engineer
Santa Clara, California, United States
$168k-$311k/yr HybridFull Time
10+ YOE10+ years verification experience, BS/MS in EE/CE/CS or equivalent, expertise in UVM/SystemVerilog/Verilog, Python and C/C++, experience with EDA tools and display protocols, strong debugging and communication skills.
UVM, SystemVerilog, Verilog, Python, C/C++, VCS, Verdi/Debussy, GDB, HLS
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Senior Verification Engineer
Santa Clara, California, United States
$168k-$311k/yr HybridFull Time
10+ YOE10+ years verification experience, strong UVM/SystemVerilog/Verilog/Python/C/C++ skills, experience with constrained-random stimulus, coverage, assertions, and EDA tools; BS/MS in EE/CE/CS or equivalent experience.
UVM, SystemVerilog, Verilog, Python, C/C++, VCS, Verdi, Debussy, GDB, HLS
2d
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Staff Engineer - Design Verification
Bengaluru or India or San Francisco or Mountain View
RemoteFull Time
8+ YOERequires 8+ years in design verification, a bachelor's or master's degree in electrical or computer engineering, and expertise in SystemVerilog, UVM, SVA, PCIe, CXL, Ethernet, and SoC/IP verification.
SystemVerilog, UVM, C, SVA, PCIe, CXL, Ethernet, UCIe, SoC, AI/ML, DDR, PowerPoint
3mo
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Physical Verification Engineer
Phoenix or Santa Clara or Hillsboro
$129k-$245k/yr HybridFull Time
3+ YOEUS citizenship, ability to obtain US government security clearance, Bachelor in Electrical/Computer Engineering or STEM, 3+ years in CMOS processes and layout verification, 3+ years in parasitic extraction and scripting
Python, Perl, Tcl, Shell, StarRC, Quantus, xACT, ICV, Calibre, Pegasus, LVS, DRC, ERC, PERC, Parasitic Extraction Tools
1w
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Design Verification Engineer
San Jose, California, United States
$120k-$200k/yr OnsiteFull Time
5+ YOEBachelor's degree in computer science, computer engineering, or related field; 5+ years' relevant experience; strong SystemVerilog and UVM proficiency; digital design, SoC architecture, verification, scripting, and simulation debugging expertise.
SystemVerilog, UVM, Python, Perl, TCL, shell scripting, Claude
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Design Verification Engineer
Aliso Viejo or San Jose or Córdoba or Toronto
OnsiteFull Time
3+ YOEBachelors in EE/CE/CS,3+ years verification experience, SystemVerilog/UVM, coverage-driven verification, C/C++ and scripting (Python,Tcl,Perl),test planning and debug skills.
SystemVerilog, UVM, C, C++, Python, Tcl, Perl
2mo
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Formal Verification Engineer
San Jose, California, United States
$150k-$350k/yr OnsiteFull Time
Deep formal verification expertise, experience with assertion-based verification and proof debugging, proficiency scripting in Python or Tcl, and hands-on use of formal EDA tools to verify RTL and production IP.
JasperGold, VC Formal, Questa Formal, SystemVerilog Assertions (SVA), Python, Tcl
2w
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Staff Design Verification Engineer
Sunnyvale, California, United States
$250k-$300k/yr OnsiteFull Time
10+ YOERequires 10+ years of design verification experience, SystemVerilog, DPI, UVM, Python or Perl, scalable testbench development, verification tools, and strong debugging skills. BS or MS in computer science or electrical engineering desired.
SystemVerilog, DPI, UVM, Python, Perl
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ASIC Verification Engineer
San Jose, California, United States
OnsiteFull Time
8+ YOE8+ years in UVM verification; RTL/gate-level verification; test plan and testbench development in C/Assembly/SystemVerilog; AMBA AXI/AHB/APB; PCIe/USB/Ethernet; scripting; repository and bug-tracking tools.
UVM, SystemVerilog, C, Assembly, Python, Shell, Perl, AMBA AXI, AHB, APB, PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART, Git, JIRA, Bitbucket, Jenkins
3w
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Digital Verification Engineer
South San Francisco, California, United States
$131k-$243k/yr OnsiteFull Time
3+ YOEMinimum 3 years digital ASIC verification experience; strong SystemVerilog; automation scripting (Python, Perl, Makefile, Tcl, UNIX shell); code coverage and regression setup; familiarity with SystemC/C++, UVM, formal and low-power verification preferred.
SystemVerilog, Python, Perl, Makefile, Tcl, UNIX shell, SystemC, C++, IEEE-1801 (UPF), UVM, ARM, RISC-V, AMBA, FPGA
1mo
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Verification CAD Engineer
Milpitas, California, United States
$160k-$265k/yr HybridFull Time
7+ YOEB.S./M.S. in EE/CE/CS,7+ years design verification experience,expert SystemVerilog/UVM and SVA/CDV,advanced Python and Shell skills,Linux and regression farm experience (LSF/NC/Slurm),familiarity with Cadence verification tools.
SystemVerilog, UVM, SVA, Python, Shell, Perl, Xcelium, SimVision, vManager, Verissium, Linux, LSF, NC, Slurm
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