613 verification engineer jobs at 156 companies in Sausalito, CA
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Verification Engineer
San Jose or Fort Collins
$120k-$192k/yr OnsiteFull Time
8+ YOEBS in Electrical/Electronic Eng or CS; 8+ years ASIC/RTL verification; SystemVerilog/UVM/OVM; Python/C++; block- and system-level verification; strong debugging and collaboration.
SystemVerilog, UVM, OVM, Python, C/C++, RTL
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Verification Engineer
San Jose, California, United States
OnsiteFull Time
3+ YOEBS/MS in ECE (or equivalent), 3+ years ASIC/SoC functional verification, strong UVM/SystemVerilog skills, testbench development, scripting in Python/Perl/TCL, and familiarity with regression/CI and hardware-assisted verification.
UVM, SystemVerilog, Python, Perl, TCL, Verilog-AMS, Palladium, Veloce, HAPS, Protium, UPF, UCIe, PCIe, CXL, Ethernet, UALink, VIP
3mo
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Principal Verification Engineer
Austin or Santa Clara
OnsiteFull Time
12+ YOE+12 years of experience; BS or MS in Computer Science, Electrical Engineering, or related field; experience with microarchitecture, CPU design, verification flow; strong analytical and troubleshooting skills; ability to collaborate across teams.
1w
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Senior Verification Engineer
Mountain View, California, United States
$120k-$235k/yr HybridFull Time
5+ YOEAdvanced degree or equivalent experience in EE/CE/CS with multi-year design verification experience; ability to pass cloud background and export-control screenings.
Universal Verification Methodology (UVM), Verilog, Zsh, Bash, Python, Perl, Advanced Microcontroller Bus Architecture (AMBA), AXI-4
3w
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Design Verification Engineer
Mountain View, California, United States
$120k-$475k/yr HybridFull Time
Concept-to-silicon verification experience; SystemVerilog, Python, C/C++, Bluespec; UVM and assertion-based verification; formal/simulated verification; portable test creation and silicon debug experience.
SystemVerilog, Python, C/C++, Bluespec, UVM, assertion-based verification (ABV)
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Design Verification Engineer
Santa Clara, California, United States
$146k-$250k/yr OnsiteFull Time
SystemVerilog/UVM verification expertise; IP/subsystem/SoC verification; testbench development; strong debugging and collaboration.
SystemVerilog, UVM, VCS, Verdi/DVE, Python, Shell, Tcl, Make
3w
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Design Verification Engineer
Mountain View, California, United States
$120k-$475k/yr HybridFull Time
Concept-to-silicon verification experience with SystemVerilog, UVM, ABV, and scripting; production verification and silicon bring-up experience preferred.
SystemVerilog, Python, C/C++, Bluespec, UVM, assertion-based verification (ABV)
2w
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Senior Verification Engineer
Santa Clara, California, United States
$168k-$311k/yr HybridFull Time
10+ YOE10+ years verification experience, BS/MS in EE/CE/CS or equivalent, expertise in UVM/SystemVerilog/Verilog, Python and C/C++, experience with EDA tools and display protocols, strong debugging and communication skills.
UVM, SystemVerilog, Verilog, Python, C/C++, VCS, Verdi/Debussy, GDB, HLS
2w
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Senior Verification Engineer
Santa Clara, California, United States
$168k-$311k/yr HybridFull Time
10+ YOE10+ years verification experience, strong UVM/SystemVerilog/Verilog/Python/C/C++ skills, experience with constrained-random stimulus, coverage, assertions, and EDA tools; BS/MS in EE/CE/CS or equivalent experience.
UVM, SystemVerilog, Verilog, Python, C/C++, VCS, Verdi, Debussy, GDB, HLS
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Physical Verification Engineer
Phoenix or Santa Clara or Hillsboro
$129k-$245k/yr HybridFull Time
3+ YOEUS citizenship, ability to obtain US government security clearance, Bachelor in Electrical/Computer Engineering or STEM, 3+ years in CMOS processes and layout verification, 3+ years in parasitic extraction and scripting
Python, Perl, Tcl, Shell, StarRC, Quantus, xACT, ICV, Calibre, Pegasus, LVS, DRC, ERC, PERC, Parasitic Extraction Tools
1d
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Design Verification Engineer
Santa Clara, California, United States
$45k-$121k/yr OnsiteFull Time
3+ YOERequires 3–5 years of experience with VLSI hardware verification, SystemVerilog, UVM, AMBA protocols, test planning, coverage analysis, simulation debugging, regressions, and power-aware verification.
SystemVerilog, UVM, AMBA, UPF, CPF, VLSI, HVL
2w
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Design Verification Engineer
Aliso Viejo or San Jose or Córdoba or Toronto
OnsiteFull Time
3+ YOEBachelors in EE/CE/CS,3+ years verification experience, SystemVerilog/UVM, coverage-driven verification, C/C++ and scripting (Python,Tcl,Perl),test planning and debug skills.
SystemVerilog, UVM, C, C++, Python, Tcl, Perl
1mo
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Design Verification Engineer
San Francisco, California, United States
OnsiteFull Time
Digital-focused design verification for pre-silicon IP: DV methodology, test-plan and verification environment development, test writing, debug, coverage, and RTL sign-off for tape-out.
1mo
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Formal Verification Engineer
San Jose, California, United States
$150k-$350k/yr OnsiteFull Time
Deep formal verification expertise, experience with assertion-based verification and proof debugging, proficiency scripting in Python or Tcl, and hands-on use of formal EDA tools to verify RTL and production IP.
JasperGold, VC Formal, Questa Formal, SystemVerilog Assertions (SVA), Python, Tcl
2mo
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ASIC Verification Engineer
San Jose, California, United States
OnsiteFull Time
8+ YOE8+ years in UVM verification; RTL/gate-level verification; test plan and testbench development in C/Assembly/SystemVerilog; AMBA AXI/AHB/APB; PCIe/USB/Ethernet; scripting; repository and bug-tracking tools.
UVM, SystemVerilog, C, Assembly, Python, Shell, Perl, AMBA AXI, AHB, APB, PCIe, USB, Ethernet, DDR3/4, LPDDR, I2C/I3C, SPI, SD/SDIO/eMMC, UART, Git, JIRA, Bitbucket, Jenkins
2w
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Verification CAD Engineer
Milpitas, California, United States
$160k-$265k/yr HybridFull Time
7+ YOEB.S./M.S. in EE/CE/CS,7+ years design verification experience,expert SystemVerilog/UVM and SVA/CDV,advanced Python and Shell skills,Linux and regression farm experience (LSF/NC/Slurm),familiarity with Cadence verification tools.
SystemVerilog, UVM, SVA, Python, Shell, Perl, Xcelium, SimVision, vManager, Verissium, Linux, LSF, NC, Slurm
2d
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Digital Verification Engineer
South San Francisco, California, United States
$131k-$243k/yr OnsiteFull Time
3+ YOEMinimum 3 years digital ASIC verification experience; strong SystemVerilog; automation scripting (Python, Perl, Makefile, Tcl, UNIX shell); code coverage and regression setup; familiarity with SystemC/C++, UVM, formal and low-power verification preferred.
SystemVerilog, Python, Perl, Makefile, Tcl, UNIX shell, SystemC, C++, IEEE-1801 (UPF), UVM, ARM, RISC-V, AMBA, FPGA
1mo
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Systems Verification Engineer I
Fremont, California, United States
$106k-$132k/yr OnsiteFull Time
0+ YOEBS in Science/Engineering/Math, 0–2 years product development/verification experience for medical devices or IVD, writing requirements, multidisciplinary engineering knowledge, flow cytometry familiarity, experience with system engineering tools.
Helix ALM, Jira, JMP, TestRail, DOORs, SpectroFlo
2d
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ASIC Verification Engineer
Sunnyvale, California, United States
$120k-$243k/yr HybridFull Time
3+ YOERequires 3+ years of ASIC/SoC verification experience, SystemVerilog and UVM expertise, test planning, coverage analysis, assertions, randomization, and simulation-tool proficiency.
SystemVerilog, UVM, Cadence Xcelium, Synopsys VCS, Mentor Questa, Jenkins, UPF
2d
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ASIC Verification Engineer
Sunnyvale, California, United States
$120k-$243k/yr HybridFull Time
3+ YOERequires 3+ years of ASIC/SoC verification experience, strong SystemVerilog and UVM expertise, and experience with test planning, coverage, assertions, simulation, and waveform debugging.
SystemVerilog, UVM, Cadence Xcelium, Synopsys VCS, Mentor Questa, Jenkins, UPF
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