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Verification Engineer
San Jose or San Diego or Austin or Longmont
$124k-$213k/yr HybridFull Time
Experience in IP/ASIC/FPGA verification using UVM, Verilog/SystemVerilog, scripting (Python/Perl), and developing test plans and regression suites; bachelor’s or master’s in computer or electrical engineering.
UVM, Verilog, System Verilog, Python, Perl, PCIe, CXL, NVMe, Ethernet, HLS
3w
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Staff Engineer - ASIC Verification
San Jose, California, United States
$139k-$259k/yr HybridFull Time
8+ YOEBachelor's in CS/EE required (Master's desired), 8+ years ASIC verification experience, fluent in System Verilog, UVM, Python/Perl, knowledge of assertions, functional/code coverage and formal verification tools, strong communication.
System Verilog, UVM, Python, Perl
3mo
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MLA Design Verification Engineer, Annapurna Labs
Austin or Cupertino
$136k-$213k/yr OnsiteFull Time
3+ YOE3+ years design verification with SystemVerilog/UVM; testbench development; experience with multiple verification platforms; scripting in Python/Perl; C/C++ OO programming.
SystemVerilog, UVM, Python, Perl, C++
2d
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Chief Systems Engineer (CSE)
Saratoga or Arlington
$190k-$225k/yr OnsiteFull Time
15+ YOE15+ years systems engineering in space, constellation experience, requirements traceability, RF/phased-array background, MBSE familiarity, and program-level verification experience.
DOORS NG, Cameo, SysML
3d
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Sr R&D Engineer, NPD
Campbell, California, United States
$132k-$158k/yr OnsiteFull Time
5+ YOEBachelor's in engineering, 5+ years in medical device or regulated industry, catheter design and design control experience, CAD (Solidworks, ProE) and Minitab proficiency, risk analysis and verification/validation experience.
Minitab, Solidworks, ProE
2mo
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R&D Engineer IC Design
San Jose, California, United States
$120k-$192k/yr OnsiteFull Time
6+ YOE6+ years in design verification; master’s in ECE/CS; SystemVerilog, scripting; UVM preferred; knowledge of networking and switching.
SystemVerilog, UVM, Scripting, Testbenches, ATE testing
2mo
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CPU Physical Design and Integration Engineer
Santa Clara, California, United States
OnsiteFull Time
BS degree; experience with place-and-route and physical verification; scripting in Perl or Tcl.
Place and Route tools, PDV, DRC/LVS, Python, Perl, Tcl
1mo
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Senior Field Security Applications Engineer
Campbell or Austin or United States
$140k-$190k/yr FieldFull Time
5+ YOE5+ years SoC design and verification experience with Verilog/VHDL/SystemVerilog, RTL simulation/emulation tools, strong presentation skills, willingness to travel, US citizenship required.
Verilog, VHDL, SystemVerilog, RTL Simulation, Emulation, Synopsys, Cadence, Siemens, Cycuity Radix, Cycuity HW, FPGA-based Prototyping
2mo
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Quality Engineer
Los Gatos, California, United States
$95k-$120k/yr OnsiteFull Time
2+ YOE2+ years engineering in medical devices; BS in Biomedical, Electrical, Mechanical or Systems Engineering; knowledge of quality, regulatory affairs, risk management, PFMEA, and design verification; on-site in Los Gatos.
Statistical analysis, Design of Experiments, PFMEA, Quality management software, Regulatory compliance
3mo
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Flight Research Staff Integrated Systems Test Engineer
Santa Cruz, California, United States
$186k-$297k/yr OnsiteFull Time
Leading system integration and verification across software and hardware; automated test frameworks; C++, Python; real-time systems; fast-paced hardware-integrated environments.
C++, Python, Bazel, CI/CD, Linux, Real-time Linux
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