New York City or San Francisco or Seoul or Copenhagen or London
$140k-$180k/yrHybridFull Time
Normal Computing: Building probabilistic AI and thermodynamic computing for semiconductor design.
5+ YOE5+ years in Digital Verification in semiconductor/EDA; SystemVerilog/UVM; EDA tools (vManager, Xcelium, Jasper); Python or Perl scripting; end-to-end verification expertise.
Tempe or Independence or Arizona or Ohio or San Jose or New York City
$142k-$224k/yrHybridFull Time
ViasatNASDAQ: VSAT: Provider of global satellite-based connectivity and secure communication solutions.
8+ YOE8+ years design verification experience with UVM and testbench development; Bachelor's in EE/CE or related; experience with Questa/Xcelium/VCS; AI/agentic DV experience preferred; US citizenship and ability to obtain Secret clearance; travel up to 10%.
8+ YOEBachelor's degree with 8+ years (or equivalent experience); eligible for Secret clearance; experience with SystemVerilog/UVM/OVM and/or VHDL, Mentor Questa or Cadence tools; FPGA/ASIC verification, test plan development, and strong communication.
Kearfott: Designs and manufactures aerospace guidance and motion control systems.
2+ YOEVerification engineer for embedded real-time software; DO-178C; C/C++; 2+ years in embedded verification; requirements-based testing; on-site in Pine Brook, NJ; US citizenship with ability to obtain clearance.
Leonardo DRSNASDAQ: DRS: Manufactures advanced electronic systems for defense and military applications.
5+ YOEBachelor’s degree in engineering or computer science; 5+ years embedded systems verification; Python and C/C++ proficiency; Agile/Scrum experience; cross-functional coordination.
Product Line Integratioin Verification & Validation Lead Engineer
Nashua or Totowa or New Hampshire or New Jersey or United States
$150k-$254k/yrOnsiteFull Time
BAE SystemsLondon Stock Exchange: BA: Designs and manufactures advanced defense and aerospace systems.
8+ YOE3+ MgmtBachelor's in a technical field, 8+ years systems testing/IV&V experience, 3+ years leadership, experience with EW/RADAR/communications preferred, ability to obtain Top Secret clearance (active Secret or higher preferred).
Harris Energy Solutions: Provides energy management and engineering consulting for buildings.
1+ YOEBachelor's in Engineering; 1-3 years in M&V/energy analytics; IPMVP/ASHRAE/FEMP knowledge; Excel required; Python/R/SQL preferred; travel within the US.
Category Labs: Developing a high-performance EVM-compatible Layer 1 blockchain protocol.
5+ YOE5+ years C++ systems engineering experience, hands-on interactive theorem prover experience (ideally Rocq/Coq), strong concurrency and memory reasoning, degree in CS or equivalent experience, clear communication and performance profiling skills.
Eos Energy EnterprisesNASDAQ: EOSE: Manufactures aqueous z-based long-duration energy storage systems.
Bachelor's in engineering required; quality engineering or new product development experience preferred. Responsibilities include root cause analysis, FMEA, verification/validation testing, supplier qualification, audits, and design control documentation.
OrganOx: Developing advanced machine perfusion technology for organ preservation.
Experience in product engineering/product development (medical device or regulated industry), electro-mechanical device testing and troubleshooting, design change and verification, ISO13485 documentation, strong written and verbal communication.
Huntsville or Exeter or Plainview or Hauppauge or Colorado Springs or Colorado
$150k-$200k/yrOnsiteFull Time
Frontgrade Technologies: Provides mission-critical electronics for space and defense applications.
10+ YOEBachelor's in Electrical or Computer Engineering, minimum 10 years experience in digital hardware design, expertise in FPGA and high-speed interfaces, signal/power integrity, schematic capture, and hardware verification.
Amsterdam or Chicago or London or New York City or Singapore
OnsiteFull Time
Headlands Technologies: A global proprietary trading firm utilizing quantitative algorithms.
Professional FPGA/ASIC design and verification experience; SystemVerilog/Verilog/VHDL and C++; familiarity with EDA tools and scripting (TCL, Python, Bash); university degree in EE/CS/CE or related.
YieldNest: Liquid restaking protocol for risk-adjusted DeFi yields.
3+ YOE3+ years in platform/infra or reliability engineering; experience building test infrastructure for payments/ledgers; familiarity with formal verification, property-based or chaos testing preferred; strong ownership of internal tooling and CI/CD.
ASMLNASDAQ: ASML: Manufactures lithography systems used to print patterns on wafers.
2+ YOEBS in a technical field with 2+ years relevant experience; Master's preferred. Experience operating and troubleshooting test rigs, integration and verification, and ability to work unsupervised. Software engineering is a plus.
Analog DevicesNASDAQ: ADI: Designs and manufactures semiconductors for signal processing and power management.
2+ YOEMaster’s degree in Electrical/Electronic/Computer Engineering or related field; 2+ years in digital design/mixed-signal verification; experience with RTL, Verilog/SystemVerilog, and ASIC/FPGA design flows.
Logiqal: Developing modular quantum computing systems using neutral atom technology.
Experienced in FPGA/ASIC digital logic design and verification, RTL and low-latency firmware for multi-domain clock systems; familiarity with Xilinx/AMD RFSoC platforms preferred.
Associate Principal Scientist, Combination Product Design Verification (Associate Director Equivalent)
Rahway, New Jersey, United States
$142k-$224k/yrOnsiteFull Time
Merck & Co.NYSE: MRK: Produces prescription medicines, vaccines, and animal health products.
8+ YOEBS +8y or MS +5y or PhD +3y in Mechanical Engineering with leadership in design verification for drug-device combos; cross-functional leadership; regulatory knowledge
Solidworks, Instron, Zwick, XRCT, Keyence, TA Instrument, 3D CAD, machining, 3D printing, ISO 11608, ISO 11040, ISO 80369, ISO 13485, ISO 14971, ISO 10993, ISTA 3A/B, ASTM F1886, ASTM D4169, ASTM F1980
Two Sigma: Systematic investment management and quantitative trading firm.
1+ YOEMinimum 1 year RTL design and verification experience, proficiency in SystemVerilog and Python, FPGA/ASIC knowledge, timing analysis, network protocol familiarity; C++ is a plus.