300 verification jobs at 87 companies in La Mesa, CA
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GSoC Design Verification Engineer
San Diego, California, United States
$99k-$148k/yr OnsiteFull Time
Bachelor's degree required; experience with SystemVerilog, UVM, C, SVA, coverage-driven verification, SoC design, Python or scripting, and AI-assisted verification workflows.
SystemVerilog, UVM, C, Python, SVA, Portable Stimulus (PSS), Veloce, Palladium, ZeBu, GPT, Claude, Llama
2d
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Lead Formal Verification Engineer
Austin or Orlando or San Diego
$156k-$268k/yr HybridFull Time
Undergraduate degree required; master's or PhD preferred. Requires formal verification expertise, SystemVerilog Assertions, EDA tools, processor architecture, verification infrastructure, and convergence techniques.
SystemVerilog Assertions (SVA), JasperGold, VC Formal, Murphi
1w
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Benefits Verification Specialist
Georgia or Malvern or Mendota Heights or San Diego
$17-$31/hr RemoteFull Time
Benefits verification and data entry experience required; Microsoft Office, Outlook, and Word proficiency; high school diploma or GED required. Healthcare, home infusion, or DME experience preferred.
Microsoft Office, Microsoft Outlook, Microsoft Word, ACIS
1w
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Design Verification Engineer
Broomfield or San Diego or Fort Collins or San Jose or Irvine
$144k-$230k/yr OnsiteFull Time
10+ YOE12+ years verification experience for complex digital and mixed-signal circuits; proficiency with SystemVerilog/UVM/SVA, scripting, simulation tools, and RTL/gate-level debug; BS/MS in EE/CE.
SystemVerilog, UVM, SVA, Synopsys, Cadence, Mentor, Perl, Python, Tcl, DesignSync, git, Palladium, Veloce, Zebu, Xilinx, ICL, PDL, Tessent
1mo
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PHY Design Verification Engineer
San Diego, California, United States
OnsiteFull Time
Work on PHY design verification, emulation, test and validation for wireless SoC development.
1w
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Sr Staff COE Verification Engineer
San Diego, California, United States
$136k-$201k/yr OnsiteFull Time
5+ YOEBachelor’s or master’s degree in electrical or computer engineering, 5–10 years of ASIC/SoC verification experience, and expertise in PCIe, CXL, SystemVerilog, and UVM; scripting experience preferred.
UVM, SystemVerilog, SystemVerilog Assertions (SVA), Python, Shell, Perl, Palladium, Veloce, UPF
5d
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TPU Design Verification Engineering Lead
Mountain View or San Diego
$192k-$278k/yr OnsiteFull Time
10+ YOE10+ MgmtBachelor's degree or equivalent practical experience; 10 years managing functional verification for IPs and SoCs. Expertise in verification methods including formal, GLS, UPF, UVM, and C-based testing.
GLS, UPF, UVM, C
2mo
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Design Verification Engineer - Viasat Government
Marlborough or Carlsbad
$133k-$210k/yr OnsiteFull Time
5+ YOEBachelor's in Electrical or Computer Engineering; 5+ years hardware verification with SystemVerilog/UVM; RTL verification; strong SystemVerilog/UVM; experience with industry EDA tools; US citizenship and active Secret clearance; willingness to travel up to 10%
SystemVerilog, UVM, Siemens Questa, Cadence, Synopsys, Mentor, Python, TCL
3w
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Senior Design Verification Engineer
Mountain View or Hillsboro or Redmond or San Diego
$120k-$235k/yr HybridFull Time
Experience creating emulation/simulation environments, verification using System Verilog/UVM, scripting (Python/Ruby/Perl), Verilog/C/C++, FPGA/emulation experience, and ability to meet export/security screening.
Zebu, Palladium, Verilog, System Verilog, UVM, C, C++, Python, Ruby, Perl, FPGAs, Makefiles
2mo
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Principal/ Sr. Principal Digital Verification Engineer
San Diego, California, United States
$125k-$235k/yr OnsiteFull Time
5+ YOEUS citizen able to obtain Secret clearance. Bachelor’s in EE or STEM required. 5+ years digital verification experience (Principal) or 8+ years (Sr. Principal). VHDL, FPGA verification, Siemens Questa, verification planning, and simulation/debug skills.
VHDL, FPGA, Siemens Questa Simulator, OSVVM, Perl, TCL, Bash, Makefile, Linux, Siemens Lint, Siemens Inspect, Siemens CDC
2mo
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Design Verification Engineer - Viasat Government
Marlborough or Carlsbad
$133k-$210k/yr OnsiteFull Time
5+ YOEBachelor's in EE/CE or related,5+ years hardware verification experience with SystemVerilog/UVM,experience with industry EDA tools,US citizenship and active Secret clearance required,ability to travel up to 10%.
SystemVerilog, UVM, Siemens Questa, Cadence, Synopsys, Mentor, AMD/Xilinx Vivado, Altera Quartus, Microchip Libero, TCL, Perl, Python, Linux
2mo
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GPU Design Verification Engineer
San Diego, California, United States
$180k-$301k/yr OnsiteFull Time
10+ YOEMS/PhD or equivalent,10+ years ASIC design verification experience,SystemVerilog/UVM,constrained random,functional coverage,hw/sw co-simulation,emulation,strong debugging and GPU architecture knowledge.
SystemVerilog, UVM, emulation
3d
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Senior Test and Verification Engineer
San Diego, California, United States
HybridFull Time
10+ YOEBachelor's degree and at least 10 years of experience in test and verification, including test planning, procedures, integration testing, validation, technical coordination, and issue resolution.
Ultra-High Frequency (UHF), UHF Follow-On (UFO), SATCOM
1mo
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Design Verification Engineer
San Diego, California, United States
$81k-$142k/yr OnsiteFull Time
3+ YOEBachelor's in engineering (or equivalent experience); 3+ years engineering experience; strong knowledge of ASME Y14.100 and Y14.5, PDM experience, ability to read/interprete drawings, lead teams, and obtain DoD clearance.
Product Data Management (PDM)
3mo
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Satellite Design Verification Engineer, Amazon Leo
Austin or Sunnyvale or Redmond or San Diego
$136k-$184k/yr OnsiteFull Time
5+ YOE2+ years UVM, C, SystemC, and scripting; 5+ years verification for communication systems; Bachelor's degree in Electrical Engineering.
UVM, C, SystemC, DPI-C, SystemVerilog, Matlab
1mo
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Senior Principal Design Verification Engineer - FPGA - (Sign-on Bonus)
San Diego or Nashua or Austin or Totowa or California or New Hampshire or Texas or New Jersey or United States
$130k-$222k/yr OnsiteFull Time
8+ YOEBachelor's degree with 8+ years (or equivalent experience); eligible for Secret clearance; experience with SystemVerilog/UVM/OVM and/or VHDL, Mentor Questa or Cadence tools; FPGA/ASIC verification, test plan development, and strong communication.
SystemVerilog, UVM, OVM, VHDL, Mentor Questa, Cadence, Perl, Python, C++, Java, Git, Jira, BitBucket, Matlab, Simulink
3w
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Principal Modem PHY IP Design Verification Engineer - Terawave
Texas or California or San Diego
$269k-$377k/yr OnsiteFull Time
Blue Origin: Develops reusable rockets and systems for human spaceflight.
10+ YOEBachelor's in EE/CE/CS,10+ years verification experience, SystemVerilog and UVM expertise, modem PHY/DSP familiarity, scripting with Python/Perl/shell, strong RTL/testbench debugging, ability to work with cross-functional teams.
SystemVerilog, UVM, Python, Perl, shell, MATLAB, C/C++
2w
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Verification & Validation Senior Test Engineer
San Diego, California, United States
$120k-$165k/yr OnsiteFull Time
10+ YOEActive SECRET clearance and U.S. citizenship,10+ years test & evaluation experience for comms systems,5+ years system engineering and integration experience,BS degree,strong analytical and communication skills.
SYSML, Dynamic Object-Oriented Requirements System (DOORS)
2w
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Verification & Validation Senior Test Engineer
San Diego, California, United States
$120k-$165k/yr OnsiteFull Time
10+ YOE10+ years T&E experience with DoD communication systems, 5+ years satellite systems engineering and integration, active SECRET clearance, bachelor\u0002s degree, strong analytical and communication skills.
SYSML, Dynamic Object-Oriented Requirements System (DOORS)
2mo
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Product Systems Engineer - Uncrewed Aircraft Systems
San Diego, California, United States
$115k-$185k/yr OnsiteFull Time
5+ YOEBachelor's in Electrical Engineering; 5+ years total with at least 3 in product systems engineering or verification; experience with UAS, RF, waveform verification.
RF design, Waveform verification, UAS
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