New Braunfels • 50 milesRemote · Hybrid · Onsite · Field · All Environments
New Braunfels • 50 milesRemote · Hybrid · Onsite · Field · All Environments
New Braunfels • 50 milesRemote · Hybrid · Onsite · Field · All Environments
New Braunfels • 50 milesRemote · Hybrid · Onsite · Field · All Environments
549 verification jobs at 145 companies in New Braunfels, TX
3d
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Digital Verification
Austin, Texas, United States
$166k/yr OnsiteFull Time
5+ YOEBachelor's degree in engineering and 5 years of progressive experience. Requires SystemVerilog, C/C++, ARM and DSP architectures, memory controllers, SoC verification, Cadence, gate-level simulation, and IP-level verification.
SystemVerilog, C, C++, ARM, DSP, Cadence, UVM
3d
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Design Verification Engineer
Santa Clara or Folsom or Austin
$166k-$250k/yr HybridFull Time
6+ YOEExperienced verification engineer with SystemVerilog, UVM, C/C++, Python or Perl, DDR memory verification, formal verification, and cross-functional hardware, firmware, and software collaboration experience.
SystemVerilog, UVM, C, C++, Python, Perl, DDR5, LPDDR5, LPDDR6, DFI, DIMMs, RTL, BIOS, GLS, NLP, XPROP, VIPs, BFMs
2mo
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Design Verification Engineer
Lakeway or Austin
OnsiteFull Time
7+ YOEBSc/MSc in engineering or CS, 7+ years verification experience, expert SystemVerilog/UVM development, protocol verification (AXI, DDRx, PCIe, USBx), verification planning, and ability to travel; eligible to work in the US.
SystemVerilog, UVM, Specman/e, C, C++, Python, Perl
2mo
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ASIC Verification Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOE5+ years verification experience, 2+ full block/system verification cycles, deep VLSI verification knowledge, experience with SystemVerilog/UVM/eRM, familiarity with data-paths/protocols (Ethernet preferred), mentoring and cross-team collaboration.
SystemVerilog, UVM, eRM, RTL, Ethernet
5d
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Director, Verification – US & Europe
Austin or Europe
$167k-$309k/yr HybridFull Time
15+ YOEBachelor's or master's degree in electrical or computer engineering; 15+ years in chip design or verification; expertise in MCU infrastructure, verification methodologies, wireless protocols, AI platforms, and team management.
RISC-V, Cursor, Claude, UPF
3mo
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Principal Verification Engineer
Austin or Santa Clara
OnsiteFull Time
12+ YOE+12 years of experience; BS or MS in Computer Science, Electrical Engineering, or related field; experience with microarchitecture, CPU design, verification flow; strong analytical and troubleshooting skills; ability to collaborate across teams.
2w
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CPU Verification Engineer
Austin, Texas, United States
$106k-$200k/yr HybridFull Time
3+ YOEDegree in EE/CE or related STEM plus 2–3+ years verification experience; expertise in SystemVerilog/UVM, scripting (Python/Perl), C++, CPU architecture knowledge, debugging and verification methodologies.
SystemVerilog, UVM, Python, Perl, C++, VCS, GIT, Assembly
2w
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Silicon Design Verification Manager
Austin, Texas, United States
$192k-$278k/yr HybridFull Time
8+ YOE8+ years verification experience, degree in EE/CS/CE, expertise in advanced verification methodologies, processor architecture, System Verilog or C++, testbench design, and simulation-based verification.
System Verilog, C++
5d
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Director, Verification – US & Europe
Austin or United States or Europe
$167k-$309k/yr HybridFull Time
15+ YOEBachelor's or master's degree in electrical or computer engineering and 15+ years in chip design or verification, with leadership, formal, functional, UPF, wireless, and MCU infrastructure expertise.
RISC-V, Cursor, Claude, UPF, AI/ML
1mo
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ASIC Engineer, Design Verification
Sunnyvale or Austin
$146k-$209k/yr OnsiteFull Time
6+ YOEBachelor's in CS/CE or equivalent; 6+ years SystemVerilog/UVM or C/C++ verification and IP/SoC level verification experience; EDA tools and scripting (Python, TCL, Perl, Shell).
SystemVerilog, UVM, C, C++, Python, TCL, Perl, Shell, Mercurial, Hg, Git, SVN, SV Assertions, Formal, Emulation, PCIe, RoCE, DDR, HBM, Ethernet
1w
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Networking Verification Engineer
Austin, Texas, United States
$124k-$242k/yr HybridFull Time
2+ YOEBachelor's degree or equivalent experience; 2+ years in software development, automation, or verification; strong Python, Linux, Git, and CI experience. Networking fundamentals and test frameworks preferred.
Python, Linux, Git, Jenkins, GitLab CI, pytest, Robot Framework, Docker, Gerrit, Grafana, Microsoft Power BI, GitHub, CI/CD
1w
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Networking Verification Engineer
Austin, Texas, United States
$124k-$242k/yr HybridFull Time
2+ YOEBachelor's degree or equivalent experience; 2+ years in software development, automation, or verification; strong Python, Linux, Git, and CI experience. Networking and test framework experience preferred.
Python, Linux, Git, Jenkins, GitLab CI, pytest, Robot Framework, Docker, Gerrit, Grafana, Power BI, GitHub
2mo
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Design Verification (DV) Engineer
Mountain View or Austin
$200k-$320k/yr OnsiteFull Time
Expert SystemVerilog and UVM verification skills; hands-on experience with logic simulators and waveform debuggers; coverage-driven verification, assertion and regression infrastructure experience; optional formal, Python/Tcl scripting, and RISC-V familiarity.
SystemVerilog, UVM, Synopsys VCS, Cadence Xcelium, Synopsys Verdi, Cadence SimVision, Python, Tcl, LLVM, RISC-V
2mo
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Digital Design Verification Engineer
Bristol or Austin
£125k/yr OnsiteFull Time
5+ YOE5+ years in digital verification for high-performance ASICs/SoCs; strong SystemVerilog, SVA, UVM, Cocotb, formal verification, CDC/RDC, and algorithm modelling (MATLAB/Simulink or Python/NumPy) skills; experience with high-speed IP (SerDes, DDR/HBM, PCIe).
SystemVerilog, UVM, SVA, CocoTB, MATLAB/Simulink, Python, NumPy, Jasper, FPGA, RTL simulation, formal verification, linting, CDC/RDC, STA, UPF, CPF, gate-level simulation
2mo
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IP Verification Engineer
Austin, Texas, United States
HybridFull Time
Several years of industry RTL verification experience, strong SystemVerilog/UVM skills, RTL testbench and TLM modeling, HW emulation experience, scripting (TCL/Python/Perl), familiarity with SerDes/PCIe/ARM/DSP/Ethernet and AMBA protocols, and BS/MS in EE/CE.
SystemVerilog, UVM, TLM, SerDes, PCIe, ARM, DSP, Ethernet, TCL, Python, Perl, C, Assembly, Linux, GIT, LSF, AMBA, APB, AXI, ACE-Lite, CHI
2w
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ASIC SoC Verification Engineer (788438)
Austin, Texas, United States
HybridFull Time
Experience in SoC/IP/SubSystem verification, SystemC/TLM and RTL environments, hardware emulation, knowledge of high-speed interfaces, strong problem-solving and communication;BS required, MS preferred.
SystemC/TLM, RTL, hardware emulation
1mo
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Formal Design Verification Engineer
Raleigh or Austin or Hillsboro or Mountain View or Redmond
$120k-$235k/yr HybridFull Time
1+ YOEDegree in EE/CS or equivalent plus technical engineering experience; formal verification, protocol and IP verification experience; ability to pass Microsoft Cloud Background Check and export-control screening.
Coherent Hub Interface (CHI), Advanced Microcontroller Bus Architecture (AMBA), PCIe, CXL, Universal Verification Methodology (UVM), System Verilog Test Bench (SVTB), Python
2mo
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Design Verification Engineer (Einfochips)
Austin or San Jose
OnsiteFull Time
6+ YOE6+ years in System Verilog HVL and C/C++, 6+ years in UVM; strong testbench development, debug, and verification closure; experience with DSP, scripting, and version control tools.
SystemVerilog, HVL, C, C++, UVM, SVTB, Make, Perl, Python, Bugzilla, Subversion
1mo
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Senior Firmware Verification Engineer
Austin, Texas, United States
OnsiteFull Time
5+ YOEBS/MS in EE or Computer Engineering required; 5+ years firmware verification experience in pre-silicon; SystemVerilog, C, Python/Perl skills; familiarity with RTL, emulation, and lab test equipment.
SystemVerilog, UVM, C, Python, Perl, RTL, FPGA, QEMU, SimVision, Verdi, oscilloscopes, power supplies, logic analyzers
3mo
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CPU Core Design Verification Test Generator Lead
Austin or Santa Clara
$100k-$500k/yr HybridFull Time
8+ YOE8+ years in CPU design verification, test generation, or related validation. Led development of test generators for x86, ARM, or RISC-V. Familiar with ISA behavior and high-performance out-of-order microarchitecture. Builds scalable verification tools and automation. Strong cross-team communication.
RISC-V, x86, ARM, automation, verification
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